Hitachi SH7750 Hardware Manual page 56

Table 1.1 SH7750 Series Features (cont)
Item
Interrupt controller
(INTC)
User break
controller (UBC)
Bus state
controller (BSC)
Rev. 6.0, 07/02, page 6 of 986
Features
•
Five independent external interrupts: NMI, IRL3 to IRL0
•
15-level encoded external interrupts: IRL3 to IRL0
•
On-chip peripheral module interrupts: Priority level can be set for each
module
•
Supports debugging by means of user break interrupts
•
Two break channels
•
Address, data value, access type, and data size can all be set as break
conditions
•
Supports sequential break function
•
Supports external memory access
 64/32/16/8-bit external data bus
•
External memory space divided into seven areas, each of up to 64
Mbytes, with the following parameters settable for each area:
 Bus size (8, 16, 32, or 64 bits)
 Number of wait cycles (hardware wait function also supported)
 Connection of DRAM, synchronous DRAM, and burst ROM possible
by setting space type
 Supports fast page mode and DRAM EDO
 Supports PCMCIA interface
 Chip select signals (CS0 to CS6) output for relevant areas
•
DRAM/synchronous DRAM refresh functions
 Programmable refresh interval
 Supports CAS-before-RAS refresh mode and self-refresh mode
•
DRAM/synchronous DRAM burst access function
•
Big endian or little endian mode can be set