Figure 4.2 Configuration Of Operand Cache(Sh7750, Sh7750S) - Hitachi SH7750 Hardware Manual

Effective address
31 26 25
OIX
22
9
MMU
19

Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S)

Rev. 6.0, 07/02, page 100 of 986
RAM area
determination
ORA
[13]
Address array
Tag U
0
511 19 bits 1 bit 1 bit
Compare
Hit signal
13 12 11 10 9
[11:5]
[12]
Longword (LW) selection
3
V
LW0 LW1 LW2
32 bits 32 bits 32 bits
Read data
5 4 3 2 1 0
Data array
LW3 LW4 LW5 LW6
32 bits 32 bits 32 bits 32 bits
Write data
LW7
32 bits