Hitachi SH7750 Hardware Manual page 31

17.3.1 Overview.............................................................................................................. 710
17.3.2 Pin Connections ................................................................................................... 711
17.3.3 Data Format ......................................................................................................... 712
17.3.4 Register Settings .................................................................................................. 713
17.3.5 Clock.................................................................................................................... 715
17.3.6 Data Transmit/Receive Operations ...................................................................... 718
17.4 Usage Notes ...................................................................................................................... 725
Section 18 I/O Ports
18.1 Overview........................................................................................................................... 731
18.1.1 Features................................................................................................................ 731
18.1.2 Block Diagrams ................................................................................................... 732
18.1.3 Pin Configuration................................................................................................. 739
18.1.4 Register Configuration......................................................................................... 741
18.2 Register Descriptions ........................................................................................................ 742
18.2.1 Port Control Register A (PCTRA) ....................................................................... 742
18.2.2 Port Data Register A (PDTRA) ........................................................................... 743
18.2.3 Port Control Register B (PCTRB) ....................................................................... 744
18.2.4 Port Data Register B (PDTRB) ............................................................................ 745
18.2.5 GPIO Interrupt Control Register (GPIOIC) ......................................................... 745
18.2.6 Serial Port Register (SCSPTR1) .......................................................................... 746
18.2.7 Serial Port Register (SCSPTR2) .......................................................................... 748
Section 19 Interrupt Controller (INTC)
19.1 Overview........................................................................................................................... 751
19.1.1 Features................................................................................................................ 751
19.1.2 Block Diagram..................................................................................................... 751
19.1.3 Pin Configuration................................................................................................. 753
19.1.4 Register Configuration......................................................................................... 753
19.2 Interrupt Sources............................................................................................................... 754
19.2.1 NMI Interrupt....................................................................................................... 754
19.2.2 IRL Interrupts ...................................................................................................... 755
19.2.3 On-Chip Peripheral Module Interrupts ................................................................ 757
19.2.4 Interrupt Exception Handling and Priority........................................................... 758
19.3 Register Descriptions ........................................................................................................ 761
19.3.1 Interrupt Priority Registers A to D (IPRA-IPRD) ............................................... 761
19.3.2 Interrupt Control Register (ICR).......................................................................... 762
19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only) ....... 764
19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only).............................. 765
19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) ............................... 766
19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) .............. 767
19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00
(SH7750R Only) .................................................................................................. 767
............................................................................................................ 731
........................................................................ 751
Rev. 6.0, 07/02, page xxxi of I