Figure 22.3 Power-On Oscillation Settling Time; Figure 22.4 Standby Return Oscillation Settling Time (Return By Reset) - Hitachi SH7750 Hardware Manual

CKIO,
internal clock
VDD
SCK2
MD8, MD7,
MD2–MD0
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 not operating
Standby
CKIO,
internal clock
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 not operating
Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET
V min
DD
t

Figure 22.3 Power-On Oscillation Settling Time

t
RESW
OSC1
t
OSCMD
t
OSC2
Stable oscillation
t
SCK2RH
t
MDRH
t
TRSTRH
Stable oscillation
t
RESW
RESET)
RESET RESET
Rev. 6.0, 07/02, page 863 of 986