Figure 4.6 Configuration Of Instruction Cache (Sh7750, Sh7750S) - Hitachi SH7750 Hardware Manual

Effective address
31 26 25 13 12 11 10 9 5 4 3 2 1 0
[11:5]
IIX
[12]
Longword (LW) selection
22
8
3
Address array Data array
Tag V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
0
MMU
19
255 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
Compare
Read data
Hit signal

Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)

Rev. 6.0, 07/02, page 109 of 986