Format Of Option Byte - NEC 78K0 Series User Manual

25.2

Format of Option Byte

The format of the option byte is shown below.
Note
Address: 0080H/1080H
7
0
WINDOW1
0
0
1
1
WDTON
0
1
WDCS2
0
0
0
0
1
1
1
1
LSROSC
0
1
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
boot swap operation.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
prohibited.
2. The watchdog timer does not stop during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
4. Be sure to clear bit 7 to 0.
Remarks 1. f : Internal low-speed oscillation clock frequency
RL
2. ( ): f = 264 kHz (MAX.)
RL
CHAPTER 25 OPTION BYTE
Figure 25-1. Format of Option Byte (1/2)
6 5
WINDOW1 WINDOW0
WINDOW0
0 25%
1 50%
0 75%
1 100%
Operation control of watchdog timer counter/illegal access detection
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS1 WDCS0
0 0 2
0 1 2
1 0 2
1 1 2
0 0 2
0 1 2
1 0 2
1 1 2
Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
Preliminary User's Manual U17260EJ3V1UD
4 3
WDTON WDCS2 WDCS1
Watchdog timer window open period
Watchdog timer overflow time
10
/f (3.88 ms)
RL
11
/f (7.76 ms)
RL
12
/f (15.52 ms)
RL
13
/f (31.03 ms)
RL
14
/f (62.06 ms)
RL
15
/f (124.12 ms)
RL
16
/f (248.24 ms)
RL
17
/f (496.48 ms)
RL
Internal low-speed oscillator operation
2 1 0
WDCS0 LSROSC
555