Interrupt Servicing Operations; Maskable Interrupt Acknowledgement - NEC 78K0 Series User Manual

19.4 Interrupt Servicing Operations

19.4.1 Maskable interrupt acknowledgement

A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1).
acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed
in Table 19-4 below.
For the interrupt request acknowledgement timing, see Figures 19-8 and 19-9.
Table 19-4. Time from Generation of Maskable Interrupt Until Servicing
When ××PR = 0
When ××PR = 1
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/f
CPU
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 19-7 shows the interrupt request acknowledgement algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into
the PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
CHAPTER 19 INTERRUPT FUNCTIONS
Minimum Time
7 clocks
8 clocks
(f : CPU clock)
CPU
Preliminary User's Manual U17260EJ3V1UD
However, a low-priority interrupt request is not
Note
Maximum Time
32 clocks
33 clocks
499