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4.5.2 Bus sizing function
The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using
the bus size configuration register (BSC).
(1) Bus size configuration register (BSC)
This register can be read/written in 16-bit units.
Cautions 1. Write to the BSC register after reset, and then do not change the set values. Also, do
not access an external memory area other than the one for this initialization routine
until the initial setting of the BSC register is complete. However, it is possible to
access external memory areas whose initial settings are complete.
2.
When the data bus width is specified as 8 bits, only the signals shown below become
active.
LWR: When accessing SRAM, external ROM, or external I/O (write cycle)
15
14
13
12
BSC
0
BS70
0
BS60
CSn signal
CS7
CS6
Note When in single-chip mode 0, 1: 5555H
When in ROMless mode 0:
When in ROMless mode 1:
Bit position
Bit name
14, 12, 10, 8,
BSn0
6, 4, 2, 0
(n = 0 to 7)
4.5.3 Word data processing format
The word data in memory can be processed using the little endian method for CS space selected with a chip select
signal (CS0 to CS7).
CHAPTER 4 BUS CONTROL FUNCTION
11
10
9
8
7
6
0
BS50
0
BS40
0
BS30
CS5
CS4
CS3
5555H
0000H
Sets the data bus width of CSn space.
BSn0
0
8 bits
1
16 bits
User's Manual U14492EJ5V0UD
5
4
3
2
1
0
0
BS20
0
BS10
0
BS00
CS2
CS1
CS0
Function
Data bus width of CSn space
Note
Address
Initial value
FFFFF066H
0000H/5555H
107
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