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18.2
Format of Option Byte
The format of the option byte is shown below.
Address: 0080H/1080H
WINDOW1
LSROSC
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
boot swap operation.
Cautions 1. The watchdog timer does not stop during self-programming of the flash memory and
2. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
3. Be sure to clear bit 7 to 0.
Remarks 1.
2.
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CHAPTER 18 OPTION BYTE
Figure 18-1. Format of Option Byte (1/2)
Note
7
6
0
WINDOW1
WINDOW0
WINDOW0
0
0
Setting prohibited
0
1
1
0
1
1
100%
WDTON
Operation control of watchdog timer counter/illegal access detection
0
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
1
Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS2
WDCS1
WDCS0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register)
1
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time taking this delay into consideration.
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
f
: Internal low-speed oscillation clock frequency
RL
( ): f
= 264 kHz (MAX.)
RL
Preliminary User's Manual U19014EJ1V0UD
5
4
3
WDTON
WDCS2
Watchdog timer window open period
Watchdog timer overflow time
10
0
2
/f
(3.88 ms)
RL
11
1
2
/f
(7.76 ms)
RL
12
0
2
/f
(15.52 ms)
RL
13
1
2
/f
(31.03 ms)
RL
14
0
2
/f
(62.06 ms)
RL
15
1
2
/f
(124.12 ms)
RL
16
0
2
/f
(248.24 ms)
RL
17
1
2
/f
(496.48 ms)
RL
Internal low-speed oscillator operation
2
1
0
WDCS1
WDCS0
LSROSC
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