NEC 78K0 Series User Manual page 175

External Input
Signal
Capture
Operation
Capture operation of CRC0n1 = 1
CR00n TI00n pin input
(reverse phase)
Interrupt signal
Capture operation of TI00n pin input
CR01n
Interrupt signal
Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit.
Caution To capture the count value of the TM0n register to the CR00n register by using the phase
reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated
after the value has been captured. If the valid edge is detected on the TI01n pin during this
operation, the capture operation is not performed but the INTTM00n signal is generated as an
external interrupt signal. To not use the external interrupt, mask the INTTM00n signal.
Remarks 1. CRC0n1: See 7.3 (2) Capture/compare control register 0n (CRC0n).
ES1n1, ES1n0, ES0n1, ES0n0: See 7.3 (4) Prescaler mode register 0n (PRM0n).
2. n = 0:
µ
n = 0, 1:
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Table 7-2. Capture Operation of CR00n and CR01n
TI00n Pin Input
Set values of ES0n1 and
ES0n0
Position of edge to be
captured
01: Rising
00: Falling
11: Both edges
(cannot be captured)
INTTM00n signal is not
generated even if value
is captured.
Note
Set values of ES0n1 and
ES0n0
Position of edge to be
captured
01: Rising
00: Falling
11: Both edges
INTTM01n signal is
generated each time
value is captured.
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Preliminary User's Manual U17260EJ3V1UD
TI01n Pin Input
CRC0n1 bit = 0 Set values of ES1n1 and
TI01n pin input ES1n0
Position of edge to be
captured
01: Rising
00: Falling
11: Both edges
INTTM00n signal is
Interrupt signal
generated each time
value is captured.
175