Multiple Exceptions - Motorola CPU32 Reference Manual

SP
(AFTER STACKING)

6.1.5 Multiple Exceptions

Each exception has been assigned a priority based on its relative importance to sys-
tem operation. Priority assignments are shown in Table 6-2. Group 0 exceptions have
the highest priorities. Group 4 exceptions have the lowest priorities. Exception pro-
cessing for exceptions that occur simultaneously is done by priority, from highest to
lowest.
Group/
Priority
0
1.1
1.2
2
3
4.1
4.2
4.3
It is important to be aware of the difference between exception processing mode and
execution of an exception handler. Each exception has an assigned vector that points
to an associated handler routine. Exception processing includes steps described in
6.1.3 Exception Processing Sequence, but does not include execution of handler
routines, which is done in normal mode.
When the CPU32 completes exception processing, it is ready to begin either exception
processing for a pending exception, or execution of a handler routine. Priority assign-
ment governs the order in which exception processing occurs, not the order in which
exception handlers are executed.
MOTOROLA
6-4
0
FORMAT
OTHER PROCESSOR STATE INFORMATION,
Figure 6-1 Exception Stack Frame
Table 6-2 Exception Priority Groups
Exception and
Relative Priority
Reset
Address Error
Bus Error
BKPT#n, CHK, CHK2,
Division by Zero, RTE,
TRAP#n, TRAPcc, TRAPV
Illegal Instruction, Line A,
Unimplemented Line F,
Privilege Violation
Trace
Hardware Breakpoint
Interrupt
EXCEPTION PROCESSING
STATUS REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
VECTOR OFFSET
DEPENDING ON EXCEPTION
(0, 2, OR 8 WORDS)
Characteristics
Aborts all processing (instruction or
exception); does not save old context
Suspends processing (instruction or
exception); saves internal context
Exception processing is a part of instruction
execution
Exception processing begins before
instruction execution
Exception processing begins when current
instruction or previous exception processing
is complete
15
CPU32
REFERENCE MANUAL