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Table of Contents

Summary of Contents for Motorola CPU32

Page 1 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
Page 3: Table Of Contents
Implicit Reference ..................3-2 Effective Address ..................3-3 3.4.1 Register Direct Mode .................3-3 3.4.1.1 Data Register Direct ..............3-3 3.4.1.2 Address Register Direct ............3-3 3.4.2 Memory Addressing Modes ...............3-4 3.4.2.1 Address Register Indirect ............3-4 CPU32 MOTOROLA REFERENCE MANUAL...
Page 4 Logic Instructions ................4-8 4.3.5 Shift and Rotate Instructions ............. 4-9 4.3.6 Bit Manipulation Instructions ............4-10 4.3.7 Binary-Coded Decimal (BCD) Instructions ........4-10 4.3.8 Program Control Instructions ............4-10 4.3.9 System Control Instructions ............4-11 MOTOROLA CPU32 REFERENCE MANUAL...
Page 5 Exception Processing Sequence ............6-3 6.1.4 Exception Stack Frame ..............6-3 6.1.5 Multiple Exceptions ................6-4 Processing of Specific Exceptions ............6-5 6.2.1 Reset ....................6-5 6.2.2 Bus Error ...................6-6 6.2.3 Address Error ..................6-7 6.2.4 Instruction Traps ................6-8 CPU32 MOTOROLA REFERENCE MANUAL...
Page 6 6.4.2 Normal Six-Word Stack Frame ............6-22 6.4.3 BERR Stack Frame ................. 6-22 SECTION 7 DEVELOPMENT SUPPORT CPU32 Integrated Development Support ..........7-1 7.1.1 Background Debug Mode (BDM) Overview ........7-1 7.1.2 Deterministic Opcode Tracking Overview ......... 7-2 7.1.3 On-Chip Hardware Breakpoint Overview .......... 7-3 Background Debug Mode (BDM) ..............
Page 7 8.1.1 Microsequencer ................. 8-1 8.1.2 Instruction Pipeline ................8-2 8.1.3 Bus Controller Resources ..............8-2 8.1.3.1 Prefetch Controller ..............8-3 8.1.3.2 Write-Pending Buffer ..............8-3 8.1.3.3 Microbus Controller ..............8-3 8.1.4 Instruction Execution Overlap ............8-4 CPU32 MOTOROLA REFERENCE MANUAL...
Page 8 Bit Manipulation Instructions ............8-20 8.3.11 Conditional Branch Instructions ............8-20 8.3.12 Control Instructions ................. 8-21 8.3.13 Exception-Related Instructions and Operations ......8-21 8.3.14 Save and Restore Operations ............8-22 APPENDIX A M68000 FAMILY SUMMARY INDEX MOTOROLA CPU32 viii REFERENCE MANUAL...
Page 9 LIST OF ILLUSTRATIONS Figure Title Page Loop Mode Instruction Sequence ..............1-3 CPU32 Block Diagram ................... 1-7 User Programming Model ................2-2 Supervisor Programming Model Supplement ..........2-2 Status Register ....................2-3 Data Organization in Data Registers .............. 2-4 Address Organization in Address Registers ........... 2-5 Memory Operand Addressing ................
Page 10 8–3 Attributed Instruction Times ................8-4 Example 1 — Instruction Stream ..............8-7 Example 2 — Branch Taken ................8-8 Example 2 — Branch Not Taken ..............8-8 Example 3 — Branch Negative Tail ............... 8-9 MOTOROLA CPU32 REFERENCE MANUAL...
Page 11 7-1 BDM Source Summary ..................7-4 7-2 Polling the BDM Entry Source ................7-5 7-3 CPU Generated Message Encoding..............7-8 7-4 BDM Command Summary................... 7-14 A-1 M68000 instruction Set Extensions ............... A-3 A-2 M68000 Addressing Modes .................. A-4 CPU32 MOTOROLA REFERENCE MANUAL...
Page 12: Table Title Page
LIST OF TABLES (Continued) Table Title Page MOTOROLA CPU32 REFERENCE MANUAL...
Page 13 CPU32. Although there are comparative references to other Motorola micro- processors throughout the manual, Section 1, Section 2, and Appendix A specifi- cally identify the CPU32 within the M68000 Family, and discuss the differences betweeen it and related devices.
Page 14 MOTOROLA CPU32 REFERENCE MANUAL...
Page 15: Features
MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance con- troller applications. The CPU32 is source code and binary code compatible with the M68000 Family.
Page 16: Virtual Memory
One of these features is the DBcc looping primitive. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by any single-word instruction that does not change the program flow. Loop mode is im- plemented in conjunction with the DBcc instruction.
Page 17: Vector Base Register
The return-from-exception (RTE) instruction uses the format code to determine what information is on the stack, so that context can be properly restored. CPU32 OVERVIEW MOTOROLA...
Page 18: Enhanced Addressing Modes
APPENDIX A M68000 FAMILY SUMMARY. 1.1.6 Instruction Set The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 1- 1). Two new instructions have been added to facilitate controller applications — low- power stop (LPSTOP) and table lookup and interpolate (TBL).
Page 19: Instruction Set Summary
Logical Shift Left and Right TBLU, TBLUN Table Lookup and Interpolate ILLEGAL Take Illegal Instruction Trap (Unsigned) Jump Test Operand and Set Jump to Subroutine TRAP Trap TRAPcc Trap Conditionally TRAPV Trap on Overflow Test Operand UNLK Unlink CPU32 OVERVIEW MOTOROLA REFERENCE MANUAL...
Page 20: Low-Power Stop Instruction
1.1.6.2 Low-Power Stop Instruction The CPU32 is a fully static design. Power consumption can be reduced to a minimum during periods of inactivity by stopping the system clock. The CPU32 instruction set includes a low-power stop command (LPSTOP) that efficiently implements this capa- bility.
Page 21: Cpu32 Block Diagram
SEQUENCER CONTROL INSTRUCTION UNIT PIPELINE DECODE DATA BUS BUS CONTROL EXECUTION CONTROL UNIT ADDRESS BUS Figure 1-2 CPU32 Block Diagram CPU32 OVERVIEW MOTOROLA REFERENCE MANUAL...
Page 22 MOTOROLA OVERVIEW CPU32 REFERENCE MANUAL...
Page 23: Architecture Summary
SECTION 2 ARCHITECTURE SUMMARY The CPU32 is upward source and object code compatible with the MC68000 and MC68010. It is downward source and object code compatible with the MC68020. With- in the M68000 Family, architectural differences are limited to the supervisory operating state.
Page 24: Registers
In addition, ad- dress registers may be used for word and long-word operations. All of the 16 general- purpose registers (D7 to D0, A7 to A0) may be used as index registers. MOTOROLA ARCHITECTURE SUMMARY CPU32 REFERENCE MANUAL...
Page 25: Data Types
Alternate function code registers SFC and DFC contain 3-bit function codes. The CPU32 generates a function code each time it accesses an address. Specific codes are assigned to each type of access. The codes can be used to select eight dedicated 4G-byte address spaces.
Page 26: Organization In Registers
There are no explicit instructions for the management of this data type; however, the MOVEM in- struction can be used to move a quad word into or out of the registers. MOTOROLA ARCHITECTURE SUMMARY CPU32 REFERENCE MANUAL...
Page 27: Address Registers
BCD data represents decimal numbers in binary form. CPU32 BCD instructions use a format in which a byte contains two digits — the four LSB contain the low digit, and the four MSB contain the high digit. The ABCD, SBCD, and NBCD instructions operate on two BCD digits packed into a single byte.
Page 28: Organization In Memory
(N + 2), and the address of the least significant byte of the long word is (N + 3). The CPU32 requires data words and long words, as well as instruction words to be aligned on word boundaries. Data misalignment is not supported. Figure 2-6 shows how operands and instructions are organized in memory.
Page 29: Memory Operand Addressing
2 BCD DIGITS = 1 BYTE 12 11 BCD 0 BCD 1 BCD 2 BCD 3 BCD 4 BCD 5 BCD 6 BCD 7 MSD = Most Significant Digit LSD = Least Significant Digit Figure 2-6 Memory Operand Addressing CPU32 ARCHITECTURE SUMMARY MOTOROLA REFERENCE MANUAL...
Page 30 MOTOROLA ARCHITECTURE SUMMARY CPU32 REFERENCE MANUAL...
Page 31: Data Organization And Addressing Capabilities
— immediate operands embedded in the instruc- tion stream and operands addressed relative to the current program counter are pro- gram space references. All operand writes are to data space. CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA...
Page 32: Notation Conventions
PC, SP CHK2 (exception) SSP, SR DBcc DIVS (exception) SSP, SR DIVU (exception) SSP, SR EORI to CCR EORI to SR PC, SP LINK LPSTOP MOVE CCR MOVE SR MOVE USP MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 REFERENCE MANUAL...
Page 33: Effective Address
In the address register direct mode, the operand is in the address register specified by the EA register field. GENERATION: EA = An ASSEMBLER SYNTAX: MODE: REGISTER: DATA REGISTER: OPERAND NUMBER OF EXTENSION WORDS: CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL...
Page 34: Memory Addressing Modes
If the address register is the stack point- er and the operand size is byte, the address is decremented by two rather than one to keep the stack pointer aligned to a word boundary. MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 REFERENCE MANUAL...
Page 35: Address Register Indirect With Displacement
The reference is classed as a data reference, except for the JMP and JSR instructions. The index operand is specified “Ri.sz*scl”. CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL...
Page 36: Address Register Indirect With Index (Base Displacement)
(bd, An, Xn. SIZE*SCALE) MODE: REGISTER: ADDRESS REGISTER: MEMORY ADDRESS BASE DISPLACEMENT: SIGN-EXTENDED VALUE SIGN-EXTENDED VALUE INDEX REGISTER: SCALE: SCALE VALUE MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 1, 2, OR 3 MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 REFERENCE MANUAL...
Page 37: Special Addressing Modes
This reference is a program space reference and is only allowed for reads. The user must include the dis- placement, the program counter, and the index register when specifying this address- ing mode. CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL...
Page 38: Program Counter Indirect With Index (Base Displacement)
The 16-bit address is sign extended to 32 bits before it is used. EA GIVEN GENERATION: ASSEMBLER SYNTAX: (xxx).W MODE: REGISTER: EXTENSION WORD: SIGN EXTENDED MEMORY ADDRESS MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 REFERENCE MANUAL...
Page 39: Absolute Long Address
Other indexed or indirect modes consist of the instruction word and the full format of extension words. The longest instruction for the CPU32 contains six extension words. It is a MOVE instruction with full format extension words for both source and destination EA and a 32-bit base displacement for both addresses.
Page 40: Effective Address Specification Formats
Table 3-1 shows categories to which each of the EA modes belong. MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3-10 REFERENCE MANUAL...
Page 41: Programming View Of Addressing Modes
#(data) 3.5.1 Addressing Capabilities In the CPU32, setting the base register suppress (BS) bit in the full format extension word (see Figure 3-2) suppresses use of the base address register in calculating the EA, allowing any index register to be used in place of the base register. Because any data register can be an index register, this provides a data register indirect form (Dn).
Page 42: Using Size In The Index Selection
USED IN ADDRESS CALCULATION Figure 3-3 Using SIZE in the Index Selection For the CPU32, the register indirect modes can be extended further. Because dis- placements can be 32 bits wide, they can represent absolute addresses or the results of expressions that contain absolute addresses. This scheme allows the general reg- ister indirect form to be (bd, Rn) or (bd, An, Rn) when the base register is not sup- pressed.
Page 43: Addressing Array Items
(SCALE = 8) (SCALE = 4) A6 = 1 A6 = 1 NOTE: Regardless of array structure, software increments index to point to next record. Figure 3-5 Addressing Array Items CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3-13...
Page 44: General Addressing Mode Summary
The user object code of earlier members of the family is upwardly compatible with later members and can be executed without change. The address extension word(s) are encoded with information that allows the CPU32 to distinguish new additions to the basic M68000 Family architecture.
Page 45: Other Data Structures
11 = Scale Factor 8 (Extension to MC68000) Figure 3-6 M68000 Family Address Extension Words The encoding for SCALE used by the CPU32 and the MC68020 is a compatible ex- tension of the M68000 architecture. A value of zero for SCALE is the same encoding for both extension words;...
Page 46: User Stacks
–(An) to pull data from the stack. In this case, after either a push or pull operation, register An points to the next available space on the stack. This scheme is illustrated as follows: MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3-16 REFERENCE MANUAL...
Page 47: Queues
After a “get” operation, the “get” register points to the last item removed from the queue, and the unchanged “put” register points to the last item placed in the queue, which is illustrated as follows: CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA...
Page 48 (if neces- sary) adjusted. The address register is adjusted by adding the buffer length (in bytes) to the register contents. MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3-18 REFERENCE MANUAL...
Page 49: Instruction Set
The CPU32 can be thought of as an intermediate member of the M68000 Family. Ob- ject code from an MC68000 or MC68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the MC68020 are also support- 4.1.1 New Instructions...
Page 50: Unimplemented Instructions
When the TBL instruction is executed, the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them. Byte, word, and long-word operand sizes are supported.
Page 51: Notation
List of registers Example: D3–D0 [...] Bits of an operand Examples: [7] is bit 7; [31:24] are bits 31 to 24 (...) Contents of a referenced location Example: (Rn) refers to the contents of Rn CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 52 BCD source operand. Least significant word Most significant word {R/W} Read/write indicator In description of an operation, a destination operand is placed to the right of source operands, and is indicated by an arrow (→). MOTOROLA INSTRUCTION SET CPU32 REFERENCE MANUAL...
Page 53: Instruction Summary
C = Decimal Borrow Z = Z • Rm •... • R0 V = Dm • Rm C = Dm V = Dm • Rm NEGX C = Dm Z = Z • Rm •... • R0 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 54: Data Movement Instructions
SP – 4 → SP, An → (SP); SP → An, SP + d → SP LINK An, #〈d〉 16, 32 〈ea〉, 〈ea〉 Source → Destination MOVE 8, 16, 32 〈ea〉, An 16, 32 → 32 Source → Destination MOVEA MOTOROLA INSTRUCTION SET CPU32 REFERENCE MANUAL...
Page 55: Integer Arithmetic Operations
〈ea〉, Dn 8, 16, 32 (Destination – Source), CCR shows results 〈ea〉, An CMPA 16, 32 (Destination – Source), CCR shows results #〈data〉, 〈ea〉 CMPI 8, 16, 32 (Destination – Data), CCR shows results CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 56: Logic Instructions
EORI 8, 16, 32 〈ea〉 Destination → Destination 8, 16, 32 〈ea〉, Dn 8, 16, 32 Destination → Destination Source Dn, 〈ea〉 8, 16, 32 #〈data〉, 〈ea〉 Destination → Destination 8, 16, 32 Data MOTOROLA INSTRUCTION SET CPU32 REFERENCE MANUAL...
Page 57: Shift And Rotate Instructions
8, 16, 32 #〈data〉, Dn 8, 16, 32 〈ea〉 ROXL Dn, Dn 8, 16, 32 #〈data〉, Dn 8, 16, 32 〈ea〉 ROXR Dn, Dn 8, 16, 32 #〈data〉, Dn 8, 16, 32 〈ea〉 SWAP CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 58: Bit Manipulation Instructions
If condition true, then PC + d → PC 8, 16, 32 Dn, 〈label〉 If condition false, then Dn – 1 → PC; DBcc if Dn ≠ (– 1), then PC + d → PC MOTOROLA INSTRUCTION SET CPU32 4-10 REFERENCE MANUAL...
Page 59: System Control Instructions
Table 4-9 System Control Operations Instruction Syntax Size Operation Privileged Data • SR → SR ANDI #〈data〉, SR Data ⊕ SR → SR EORI #〈data〉, SR 〈ea〉, SR Source → SR MOVE SR → Destination SR, 〈ea〉 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-11...
Page 60: Condition Tests
For example, the T condition is always true, and the EQ condition is true only if the Z bit condition code is true. Table 4-10 lists each condition test. MOTOROLA INSTRUCTION SET CPU32 4-12 REFERENCE MANUAL...
Page 61: Condition Tests
4.4 Instruction Details The following paragraphs contain detailed information about each instruction in the CPU32 instruction set. The instruction descriptions are arranged alphabetically by in- struction mnemonic. Figure 4-2 shows the format of the instruction descriptions. 4.2.1 Notation applies, with the following additions.
Page 62: Instruction Description Format
1 - the operation is memory to mem Register Ry field - Specifies the sourc If R/M = 0, specifies a data regist If R/M = 1, specifies an address Figure 4-2 Instruction Description Format MOTOROLA INSTRUCTION SET CPU32 4-14 REFERENCE MANUAL...
Page 63 Normally the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations. Instruction Format: REGISTER Rx REGISTER Ry CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-15...
Page 64 1 — the operation is memory to memory Register Ry field — Specifies the source register: If R/M = 0, specifies a data register If R/M = 1, specifies an address register for predecrement addressing mode MOTOROLA INSTRUCTION SET CPU32 4-16 REFERENCE MANUAL...
Page 65 EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Instruction Fields: Register field — Specifies any of the eight data registers. Opmode field: Byte Word Long Operation 〈ea〉 + 〈Dn〉 → 〈Dn〉 〈Dn〉 + 〈ea〉 → 〈ea〉 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-17...
Page 66 1. Dn mode is used when destination is a data register. Destination 〈ea〉 mode is invalid for a data register. 2. ADDA is used when the destination is an address register. ADDI and ADDQ are used when the source is immediate data. Most assemblers automatically make this distinction. MOTOROLA INSTRUCTION SET CPU32 4-18 REFERENCE MANUAL...
Page 67 Reg. number: An – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-19...
Page 68 WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Instruction Fields: Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation MOTOROLA INSTRUCTION SET CPU32 4-20 REFERENCE MANUAL...
Page 69 If size = 00, the data is the low-order byte of the immediate word. If size = 01, the data is the entire immediate word. If size = 10, the data is the next two immediate words. CPU32 INSTRUCTION SET MOTOROLA...
Page 70 Set if an overflow occurs. Cleared otherwise. Set if a carry occurs. Cleared otherwise. The condition codes are not affected when the destination is an address register. Instruction Format: EFFECTIVE ADDRESS DATA SIZE MODE REGISTER MOTOROLA INSTRUCTION SET CPU32 4-22 REFERENCE MANUAL...
Page 71 – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) *Word and long only CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-23...
Page 72 Normally the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations. Instruction Format: REGISTER Rx SIZE REGISTER Ry MOTOROLA INSTRUCTION SET CPU32 4-24 REFERENCE MANUAL...
Page 73 1 — The operation is memory to memory. Register Ry field — Specifies the source register: If R/M = 0, specifies a data register. If R/M = 1, specifies an address register for predecrement addressing mode. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 74 EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Instruction Fields: Register field — Specifies any of the eight data registers. Opmode field: Byte Word Long Operation (〈ea〉) •(〈Dn〉) → Dn (〈Dn〉) • (〈ea〉) → ea MOTOROLA INSTRUCTION SET CPU32 4-26 REFERENCE MANUAL...
Page 75 1. The Dn mode is used when the destination is a data register; the destination 〈ea〉 mode is invalid for a data register. 2. Most assemblers use ANDI when the source is immediate data. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 76 WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Instruction Fields: Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation MOTOROLA INSTRUCTION SET CPU32 4-28 REFERENCE MANUAL...
Page 77 If size = 00, the data is the low-order byte of the immediate word. If size = 01, the data is the entire immediate word. If size = 10, the data is the next two immediate words. CPU32 INSTRUCTION SET MOTOROLA...
Page 78 Cleared if bit 2 of immediate operand is zero. Unchanged otherwise. Cleared if bit 1 of immediate operand is zero. Unchanged otherwise. Cleared if bit 0 of immediate operand is zero. Unchanged otherwise. Instruction Format: BYTE DATA (8 BITS) MOTOROLA INSTRUCTION SET CPU32 4-30 REFERENCE MANUAL...
Page 79 Cleared if bit 2 of immediate operand is zero. Unchanged otherwise. Cleared if bit 1 of immediate operand is zero. Unchanged otherwise. Cleared if bit 0 of immediate operand is zero. Unchanged otherwise. Instruction Format: WORD DATA CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-31...
Page 80 For ASR, the operand is shifted right; the number of positions shifted is the shift count. Bits shifted out of the low-order bit go to both the carry and the extend bits; the sign- bit (MSB) is shifted into the high-order bit. MOTOROLA INSTRUCTION SET CPU32 4-32 REFERENCE MANUAL...
Page 81 01 — Word operation 10 — Long operation i/r field: If i/r = 0, specifies immediate shift count. If i/r = 1, specifies register shift count. Register field — Specifies a data register to be shifted. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-33...
Page 82 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-34 REFERENCE MANUAL...
Page 83 Z; N • V; N • V Less or Equal 1111 Overflow Set 1001 Condition Codes: Not affected. Instruction Format: CONDITION 8-BIT DISPLACEMENT 16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00 32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-35...
Page 84 32-Bit Displacement field — Used for displacement when 8-bit displacement field contains $FF. NOTE A branch to the instruction immediately following automatically uses 16-bit displacement because the 8-bit displacement field contains $00 (zero offset). MOTOROLA INSTRUCTION SET CPU32 4-36 REFERENCE MANUAL...
Page 85 — Not affected Not affected Set if the bit tested is zero. Cleared otherwise Not affected Not affected Instruction Format (Bit Number Static, specified as immediate data): EFFECTIVE ADDRESS MODE REGISTER BIT NUMBER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-37...
Page 86 Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — *Long only; all others are byte only MOTOROLA INSTRUCTION SET CPU32 4-38 REFERENCE MANUAL...
Page 87 — Not affected Not affected Set if the bit tested is zero. Cleared otherwise Not affected Not affected Instruction Format (Bit Number Static, specified as immediate data): EFFECTIVE ADDRESS MODE REGISTER BIT NUMBER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-39...
Page 88 Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — *Long only; all others are byte only MOTOROLA INSTRUCTION SET CPU32 4-40 REFERENCE MANUAL...
Page 89 The vector number is generated to reference the illegal instruction exception vector. Background mode is covered in SECTION 7 DEVEL- OPMENT SUPPORT. Condition Codes: — — — — — Not affected Not affected Not affected Not affected Not affected Instruction Format: CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-41...
Page 90 Typically, this instruction replaces an instruction in a program and the replaced instruction is returned by the breakpoint acknowledge cycle. Condition Codes: Not affected. Instruction Format: VECTOR Instruction Fields: Vector field — Contains immediate data in the range (0–7). This is the breakpoint number. MOTOROLA INSTRUCTION SET CPU32 4-42 REFERENCE MANUAL...
Page 91 32-Bit Displacement field — Used for a larger displacement when 8-bit displacement is $FF. NOTE A branch to the instruction immediately following automatically uses 16-bit displacement because the 8-bit displacement field contains $00 (zero offset). CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-43...
Page 92 — Not affected. Not affected Set if the bit tested is zero. Cleared otherwise Not affected Not affected. Instruction Format (Bit Number Static, specified as immediate data): EFFECTIVE ADDRESS MODE REGISTER BIT NUMBER MOTOROLA INSTRUCTION SET CPU32 4-44 REFERENCE MANUAL...
Page 93 Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — *Long only; all others are byte only CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-45...
Page 94 32-Bit Displacement field — Used for larger displacement when 8-bit displacement is $FF. NOTE A branch to the instruction immediately following automatically uses 16-bit displacement because the 8-bit displacement field contains $00 (zero offset). MOTOROLA INSTRUCTION SET CPU32 4-46 REFERENCE MANUAL...
Page 95 — Not affected. Not affected. Set if the bit tested is zero. Cleared otherwise. Not affected. Not affected. Instruction Format (Bit Number Static, specified as immediate data): EFFECTIVE ADDRESS MODE REGISTER BIT NUMBER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-47...
Page 96 Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) *Long only; all others are byte only MOTOROLA INSTRUCTION SET CPU32 4-48 REFERENCE MANUAL...
Page 97 Size field — Specifies the size of the operation. 11 — Word operation. 10 — Long operation. Effective Address field — Specifies the upper bound operand. Only data addressing modes areallowed as shown: CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-49...
Page 98 Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) *Long only; all others are byte only MOTOROLA INSTRUCTION SET CPU32 4-50 REFERENCE MANUAL...
Page 99 CHK instruction exception, vector number 6, occurs. Condition Codes: — Not affected. Undefined. Set if Rn is equal to either bound. Cleared otherwise. Undefined. Set if Rn is out of bounds. Cleared otherwise. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-51...
Page 100 D/A field — Specifies whether an address register or data register is to be checked. 0 — Data register. 1 — Address register. Register field — Specifies the address or data register that contains the value to be checked. MOTOROLA INSTRUCTION SET CPU32 4-52 REFERENCE MANUAL...
Page 101 Always cleared. Always cleared. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER Instruction Fields: Size field — Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-53...
Page 102 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-54 REFERENCE MANUAL...
Page 103 Set if a borrow occurs. Cleared otherwise. Instruction Format: EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Instruction Fields: Register field — Specifies the destination data register. Opmode field: Byte Word Long Operation (〈Dn〉) − (〈ea〉) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-55...
Page 104 CMPA is used when the destination is an address register. CMPI is used when the source is immediate data. CMPM is used for memory- to-memory compares. Most assemblers automatically make the dis- tinction. MOTOROLA INSTRUCTION SET CPU32 4-56 REFERENCE MANUAL...
Page 105 Opmode field — Specifies the size of the operation: 011 — Word operation. The source operand is sign-extended to a long oper- and and the operation is performed on the address register using all 32 bits. 111 — Long operation. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 106 Reg. number: An – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) MOTOROLA INSTRUCTION SET CPU32 4-58 REFERENCE MANUAL...
Page 107 WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Instruction Fields: Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-59...
Page 108 If size = 00, the data is the low-order byte of the immediate word. If size = 01, the data is the entire immediate word. If size = 10, the data is the next two immediate words. MOTOROLA INSTRUCTION SET CPU32 4-60 REFERENCE MANUAL...
Page 109 Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation Register Ay field — (always the source). Specifies an address register in the postin- crement addressing mode. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-61...
Page 110 Condition Codes: — Not affected. Undefined. Set if Rn is equal to either bound. Cleared otherwise. Undefined. Set if Rn is out of bounds. Cleared otherwise. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER REGISTER MOTOROLA INSTRUCTION SET CPU32 4-62 REFERENCE MANUAL...
Page 111 D/A field — Specifies whether an address register or data register is compared. 0 — Data register. 1 — Address register. Register field — Specifies the address or data register that contains the value to be checked. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-63...
Page 112 1110 N • V • Z; N • V • Z Greater Than Always true 0000 C • Z High 0010 Overflow Clear 1000 Z; N • V; N • V Less or Equal 1111 Overflow Set 1001 Condition Codes: Not affected. MOTOROLA INSTRUCTION SET CPU32 4-64 REFERENCE MANUAL...
Page 113 However, when entering a loop by branching to the trailing DBcc instruction, the control count should equal the loop execution count so that the DBcc instruction will not branch and the main loop will not execute if a zero count occurs. CPU32 INSTRUCTION SET MOTOROLA...
Page 114 Two special conditions may arise during the operation: 1. Division by zero causes a trap. 2. Overflow may be detected before instruction completion. If an overflow is detected, the overflow condition code is set and the operands are unaffect- MOTOROLA INSTRUCTION SET CPU32 4-66 REFERENCE MANUAL...
Page 115 Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) NOTE Overflow occurs if the quotient is larger than a 16-bit signed integer. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-67...
Page 116 Dq are the same register, only the quotient is returned. If Size is 1, the Dr field also specifies the data register that contains the high-order 32 bits of the dividend. NOTE Overflow occurs if the quotient is larger than a 32-bit signed integer. MOTOROLA INSTRUCTION SET CPU32 4-68 REFERENCE MANUAL...
Page 117 Set if quotient is zero. Cleared otherwise. Undefined if overflow or divide by zero occurs. Set if division overflow occurs; undefined if divide by zero occurs. Cleared oth- erwise. Always cleared. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-69...
Page 118 Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) NOTE Overflow occurs if the quotient is larger than a 16-bit signed integer. MOTOROLA INSTRUCTION SET CPU32 4-70 REFERENCE MANUAL...
Page 119 Dq are the same register, only the quotient is returned. If Size is 1, this field also specifies the data register that contains the high-order 32 bits of the dividend. NOTE Overflow occurs if the quotient is larger than a 32-bit signed integer. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-71...
Page 120 Always cleared. Instruction Format: EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Instruction Fields: Register field — Specifies any of the eight data registers. Opmode field: Byte Word Long Operation (〈ea〉) ⊕ (〈Dn〉) → 〈ea〉 MOTOROLA INSTRUCTION SET CPU32 4-72 REFERENCE MANUAL...
Page 121 — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — NOTE Memory to data register operations are not allowed. Most assem- blers use EORI when the source is immediate data. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-73...
Page 122 WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Instruction Fields: Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation MOTOROLA INSTRUCTION SET CPU32 4-74 REFERENCE MANUAL...
Page 123 If size = 00, the data is the low-order byte of the immediate word. If size = 01, the data is the entire immediate word. If size = 10, the data is next two immediate words. CPU32 INSTRUCTION SET MOTOROLA...
Page 124 Changed if bit 2 of immediate operand is one. Unchanged otherwise. Changed if bit 1 of immediate operand is one. Unchanged otherwise. Changed if bit 0 of immediate operand is one. Unchanged otherwise. Instruction Format: BYTE DATA (8 BITS) MOTOROLA INSTRUCTION SET CPU32 4-76 REFERENCE MANUAL...
Page 125 Changed if bit 2 of immediate operand is one. Unchanged otherwise. Changed if bit 1 of immediate operand is one. Unchanged otherwise. Changed if bit 0 of immediate operand is one. Unchanged otherwise. Instruction Format: WORD DATA (16 BITS) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-77...
Page 126 Register Ry field — Specifies either a data register or an address register depending on the mode. If the exchange is between data and address registers, this field always specifies the address register. MOTOROLA INSTRUCTION SET CPU32 4-78 REFERENCE MANUAL...
Page 127 010 — Sign-extend low-order byte of data register to word. 011 — Sign-extend low-order word of data register to long. 111 — Sign-extend low-order byte of data register to long. Register field — Specifies the data register is to be sign-extended. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 128 Forces an illegal instruction exception, vector number 4. All other illegal instruction bit patterns are reserved for future extension of the instruction set and should not be used to force an exception. Condition Codes: Not affected Instruction Format: MOTOROLA INSTRUCTION SET CPU32 4-80 REFERENCE MANUAL...
Page 129 (An) + — — – (An) — — , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-81...
Page 130 (An) + — — – (An) — — , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) MOTOROLA INSTRUCTION SET CPU32 4-82 REFERENCE MANUAL...
Page 131 (An) + — — – (An) — — , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-83...
Page 132 Displacement field — Specifies the twos complement integer to be added to the stack pointer. NOTE LINK and UNLK can be used to maintain a linked list of local data and parameter areas on the stack for nested subroutine calls. MOTOROLA INSTRUCTION SET CPU32 4-84 REFERENCE MANUAL...
Page 133 An external reset always initiates reset exception processing. Condition Codes: Set according to the immediate operand. Instruction Format: IMMEDIATE DATA Instruction Fields: Immediate field — Specifies the data to be loaded into the status register. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-85...
Page 134 The LSR instruction shifts the operand to the right the number of positions specified as the shift count. Bits shifted out of the low-order bit go to both the carry and the ex- tend bits; zeros are shifted into the high-order bits. MOTOROLA INSTRUCTION SET CPU32 4-86 REFERENCE MANUAL...
Page 135 01 — Word operation 10 — Long operation i/r field: If i/r = 0, specifies immediate shift count. If i/r = 1, specifies register shift count. Register field — Specifies a data register to be shifted. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-87...
Page 136 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-88 REFERENCE MANUAL...
Page 137 EFFECTIVE ADDRESS SIZE REGISTER MODE MODE REGISTER Instruction Fields: Size field — Specifies the size of the operand to be moved: 01 — Byte operation 11 — Word operation 10 — Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-89...
Page 138 *For byte size operation, address register direct is not allowed. NOTES: 1. Most assemblers use MOVEA when the destination is an address register. 2. MOVEQ can be used to move an immediate 8-bit value to a data register. MOTOROLA INSTRUCTION SET CPU32 4-90 REFERENCE MANUAL...
Page 139 Reg. number: An – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-91...
Page 140 Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — NOTE MOVE from CCR is a word operation. ANDI, ORI, and EORI to CCR are byte operations. MOTOROLA INSTRUCTION SET CPU32 4-92 REFERENCE MANUAL...
Page 141 Set to the value of bit 2 of the source operand. Set to the value of bit 1 of the source operand. Set to the value of bit 0 of the source operand. Instruction Format: EFFECTIVE ADDRESS MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-93...
Page 142 , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) NOTE MOVE to CCR is a word operation. ANDI, ORI, and EORI to CCR are byte operations. MOTOROLA INSTRUCTION SET CPU32 4-94 REFERENCE MANUAL...
Page 143 , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — NOTE Use the MOVE from CCR instruction to access only the condition codes. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-95...
Page 144 Reg. number: An – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) MOTOROLA INSTRUCTION SET CPU32 4-96 REFERENCE MANUAL...
Page 145 — Specifies the direction of transfer: 0 — Transfer the address register to the USP. 1 — Transfer the USP to the address register. Register field — Specifies the address register for the operation. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 146 Control Register field — Specifies the control register. Control Register Source Function Code (SFC) Destination Function Code (DFC) User Stack Pointer (USP) Vector Base Register (VBR) Any other code causes an illegal instruction exception. MOTOROLA INSTRUCTION SET CPU32 4-98 REFERENCE MANUAL...
Page 147 The order of loading is the same as that of control mode addressing. When the instruction has completed, the incremented address register contains the address of the last operand loaded plus the operand length. In the CPU32, if the addressing register is also loaded from memory, the value loaded is the value fetched plus the operand length.
Page 148 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-100 REFERENCE MANUAL...
Page 149 For predecrement mode addresses, the mask correspondence is reversed: NOTE An extra read bus cycle occurs for memory operands. This accesses an operand at one address higher than the last register image re- quired. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-101...
Page 150 8- or 32-bit bus. Example: Long transfer to/from an even address. Byte Organization in Register HIGH ORDER MID-UPPER MID-LOWER LOW ORDER Byte Organization in Memory (Low Address at Top) HIGH ORDER MID-UPPER MID-LOWER LOW ORDER MOTOROLA INSTRUCTION SET CPU32 4-102 REFERENCE MANUAL...
Page 151 111 — Transfer long from register to memory. Address Register field — Specifies the address register which is used in the address register indirect plus displacement addressing mode. Displacement field — Specifies the displacement used in the operand address. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 152 Always cleared. Always cleared. Instruction Format: REGISTER DATA Instruction Fields: Register field — Specifies the data register to be loaded. Data field — Eight bits of data, which are sign-extended to a long operand. MOTOROLA INSTRUCTION SET CPU32 4-104 REFERENCE MANUAL...
Page 153 Not affected. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER REGISTER Instruction Fields: Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-105...
Page 154 For either of the two following examples, which use the same ad- dress register as both source and destination, the value stored is un- defined. The current implementations of the MC68010, CPU32, and MC68020 store the incremented or decremented value of An.
Page 155 Overflow (V = 1) can occur only when multiplying 32-bit operands to yield a 32-bit result. Overflow occurs if the high-order 32 bits of the quad word product are not the sign extension of the low-order 32 bits. CPU32 INSTRUCTION SET MOTOROLA...
Page 156 Reg. number: An – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) MOTOROLA INSTRUCTION SET CPU32 4-108 REFERENCE MANUAL...
Page 157 Register Dh field — If Size is 1, specifies the data register into which the high-order 32 bits of the product are loaded. If Dh = Dl and Size is 1, the results of the operation are undefined. This field is unused, otherwise. CPU32 INSTRUCTION SET MOTOROLA...
Page 158 Overflow (V=1) can occur only when multiplying 32-bit operands to yield a 32-bit result. Overflow occurs if any of the high-order 32 bits of the quad word product are not equal to zero. MOTOROLA INSTRUCTION SET CPU32 4-110 REFERENCE MANUAL...
Page 159 Reg. number: An – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-111...
Page 160 Register Dh field — If Size is 1, specifies the data register into which the high-order 32 bits of the product are loaded. If Dh = Dl and Size is 1, the results of the operation are undefined. MOTOROLA INSTRUCTION SET CPU32 4-112 REFERENCE MANUAL...
Page 161 Normally the Z condition code bit is set via programming before the start of the operation. This allows successful tests for zero results upon completion of multiple precision operations. Instruction Format: EFFECTIVE ADDRESS MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-113...
Page 162 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-114 REFERENCE MANUAL...
Page 163 Cleared if the result is zero. Set otherwise. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER Instruction Fields: Size field — Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-115...
Page 164 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-116 REFERENCE MANUAL...
Page 165 Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER Instruction Fields: Size field — Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-117...
Page 166 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-118 REFERENCE MANUAL...
Page 167 Execution continues with the instruction fol- lowing the NOP instruction. The NOP instruction does not begin execution until all pending bus cycles are completed. This synchronizes the pipeline, and prevents instruction overlap. Condition Codes: Not affected. Instruction Format: CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-119...
Page 168 Always cleared. Always cleared. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER Instruction Fields: Size field — Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation MOTOROLA INSTRUCTION SET CPU32 4-120 REFERENCE MANUAL...
Page 169 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-121...
Page 170 EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Instruction Fields: Register field — Specifies any of the eight data registers. Opmode field: Byte Word Long Operation (〈ea〉) + (〈Dn〉) → Dn (〈Dn〉) + (〈ea〉) → ea MOTOROLA INSTRUCTION SET CPU32 4-122 REFERENCE MANUAL...
Page 171 NOTES: 1. If the destination is a data register, it must be specified using the destination Dn mode, not the destination 〈ea〉 mode. 2. Most assemblers use ORI when the source is immediate data. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 172 WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Instruction Fields: Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation MOTOROLA INSTRUCTION SET CPU32 4-124 REFERENCE MANUAL...
Page 173 If size = 00, the data is the low-order byte of the immediate word. If size = 01, the data is the entire immediate word. If size = 10, the data is the next two immediate words. CPU32 INSTRUCTION SET MOTOROLA...
Page 174 Set if bit 2 of immediate operand is zero. Unchanged otherwise. Set if bit 1 of immediate operand is zero. Unchanged otherwise. Set if bit 0 of immediate operand is zero. Unchanged otherwise. Instruction Format: BYTE DATA (8 BITS) MOTOROLA INSTRUCTION SET CPU32 4-126 REFERENCE MANUAL...
Page 175 Set if bit 2 of immediate operand is zero. Unchanged otherwise. Set if bit 1 of immediate operand is zero. Unchanged otherwise. Set if bit 0 of immediate operand is zero. Unchanged otherwise. Instruction Format: WORD DATA CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-127...
Page 176 (An) + — — – (An) — — , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) MOTOROLA INSTRUCTION SET CPU32 4-128 REFERENCE MANUAL...
Page 177 Asserts the RESET signal for 512 clock periods, resetting all exter- nal devices. The processor state, other than the program counter, is unaffected and execution continues with the next instruction. Condition Codes: Not affected. Instruction Format: CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-129...
Page 178 The ROR instruction rotates the bits of the operand to the right; the rotate count deter- mines the number of bit positions rotated. Bits rotated out of the low-order bit go to the carry bit and also back into the high-order bit. MOTOROLA INSTRUCTION SET CPU32 4-130 REFERENCE MANUAL...
Page 179 Register field — Specifies a data register to be rotated NOTE Byte swapping in the low order word of a data register is best done with ROR/ROR, W #〈8〉, Dn. A special hardware assist has been pro- vided to minimize operation execution. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-131...
Page 180 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — MOTOROLA INSTRUCTION SET CPU32 4-132 REFERENCE MANUAL...
Page 181 Bits rotated out of the low-order bit go to the carry bit and the extend bit; the previous value of the extend bit rotates into the high-order bit. ROXR CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 182 10 — Long operation i/r field — Specifies the rotate count location: If i/r = 0, immediate rotate count If i/r = 1, register rotate count Register field — Specifies a data register to be rotated MOTOROLA INSTRUCTION SET CPU32 4-134 REFERENCE MANUAL...
Page 183 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-135...
Page 184 Condition Codes: Not affected. Instruction Format: DISPLACEMENT (16 BITS) Instruction Field: Displacement field — Specifies the twos complement integer to be sign extended and added to the stack pointer. MOTOROLA INSTRUCTION SET CPU32 4-136 REFERENCE MANUAL...
Page 185 1010 — MC68020 Short Format, removes 16 words and resumes instruction execution. 1011 — MC68020 Long Format, removes 46 words and resumes instruction execution. Any other value in this field causes the processor to take a format error exception. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-137...
Page 186 Pulls the condition code and program counter values from the stack. The previous condition codes and program counter values are lost. The supervisor portion of the status register is unaffected. Condition Codes: Set to the condition codes from the stack. Instruction Format: MOTOROLA INSTRUCTION SET CPU32 4-138 REFERENCE MANUAL...
Page 187 (SP) → PC; SP + 4 → SP Operation: Assembler Syntax: Attributes: Unsized Description: Pulls the program counter value from the stack. The previous value is lost. Condition Codes: Not affected. Instruction Format: CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-139...
Page 188 1 — The operation is memory to memory. Register Dx/Ax field — Specifies the source register: If R/M = 0, specifies a data register. If R/M = 1, specifies an address register for the predecrement addressing mode. MOTOROLA INSTRUCTION SET CPU32 4-140 REFERENCE MANUAL...
Page 189 C • Z High 0010 Overflow Clear 1000 Z; N • V; N • V Less or Equal 1111 Overflow Set 1001 Condition Codes: Not affected. Instruction Format: EFFECTIVE ADDRESS CONDITION MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-141...
Page 190 A subsequent NEG.B instruction with the same effective address can be used to change the Scc result from TRUE or FALSE to the equiv- alent arithmetic value (TRUE = 1, FALSE = 0). MOTOROLA INSTRUCTION SET CPU32 4-142 REFERENCE MANUAL...
Page 191 External reset always initiates reset exception process- ing. Condition Codes: Set according to the immediate operand. Instruction Format: IMMEDIATE DATA Instruction Fields: Immediate field — Specifies the data to be loaded into the status register. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-143...
Page 192 EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Instruction Fields: Register field — Specifies any of the eight data registers. Opmode field: Byte Word Long Operation (〈ea〉) – (〈Dn〉) → 〈Dn〉 (〈Dn〉) – (〈ea〉) → 〈ea〉 MOTOROLA INSTRUCTION SET CPU32 4-144 REFERENCE MANUAL...
Page 193 1. If the destination is a data register, it must be specified as a destination Dn address, not as a destination 〈ea〉 address. 2. Most assemblers use SUBA when the destination is an address register, and SUBI or SUBQ when the source is immediate data. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 194 Reg. number: An – (An) Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) MOTOROLA INSTRUCTION SET CPU32 4-146 REFERENCE MANUAL...
Page 195 Set if an overflow occurs. Cleared otherwise. Set if a borrow occurs. Cleared otherwise. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-147...
Page 196 If size = 00, the data is the low-order byte of the immediate word. If size = 01, the data is the entire immediate word. If size = 10, the data is the next two immediate words. MOTOROLA INSTRUCTION SET CPU32 4-148 REFERENCE MANUAL...
Page 197 Set if the result is negative. Cleared otherwise. Set if the result is zero. Cleared otherwise. Set if an overflow occurs. Cleared otherwise. Set if a borrow occurs. Cleared otherwise. Instruction Format: EFFECTIVE ADDRESS DATA SIZE MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-149...
Page 198 , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — *Word and long only MOTOROLA INSTRUCTION SET CPU32 4-150 REFERENCE MANUAL...
Page 199 Set if a carry occurs. Cleared otherwise. NOTE Normally the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-151...
Page 200 1 — The operation is memory to memory. Register Dx/Ax field — Specifies the source register: If R/M = 0, specifies a data register. If R/M = 1, specifies an address register for the predecrement addressing mode. MOTOROLA INSTRUCTION SET CPU32 4-152 REFERENCE MANUAL...
Page 201 Set if the most significant bit of the 32-bit result is set. Cleared otherwise. Set if the 32-bit result is zero. Cleared otherwise. Always cleared. Always cleared. Instruction Format: REGISTER Instruction Fields: Register field — Specifies the data register to swap. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-153...
Page 202 For this mode, only the fractional portion, Dx [7:0], is used in the interpolation, and the integer portion, Dx [15:8], is ignored. The register interpolation mode may be used with several table lookup and interpolations to model multidimensional functions. MOTOROLA INSTRUCTION SET CPU32 4-154 REFERENCE MANUAL...
Page 203 16 15 BYTE SIGN EXTENDED SIGN EXTENDED RESULT FRACTION WORD SIGN EXTENDED RESULT RESULT FRACTION LONG RESULT RESULT RESULT FRACTION NOTE A long-word result contains only the least significant 24 bits of integer precision. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-155...
Page 204 Set if the integer portion of an unrounded long result is not in the range, – (2 ≤ Result ≤ (2 ) – 1. Cleared otherwise. Always cleared. Instruction Format: Table lookup and interpolate: EFFECTIVE ADDRESS MODE REGISTER REGISTER Dx SIZE MOTOROLA INSTRUCTION SET CPU32 4-156 REFERENCE MANUAL...
Page 205 Rounding mode field: The ’R’ bit controls rounding of the final result. When R = 0, the result is rounded according to the round-to-nearest algorithm. When R = 1, the result is returned unrounded. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 206 For this mode, only the fractional portion, Dx [7:0], is used in the interpolation, and the integer portion, Dx [15:8], is ignored. The register interpolation mode may be used with several table lookup and interpolations to model multidimensional functions. MOTOROLA INSTRUCTION SET CPU32 4-158 REFERENCE MANUAL...
Page 207 16 15 BYTE ZERO EXTENDED ZERO EXTENDED RESULT FRACTION WORD ZERO EXTENDED RESULT RESULT FRACTION LONG RESULT RESULT RESULT FRACTION NOTE A long-word result contains only the least significant 24 bits of integer precision. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-159...
Page 208 Set if the integer portion of an unrounded long result is not in the range,0 ≤ Result ≤ (2 ) – 1. Cleared otherwise. Always cleared. Instruction Format: Table Lookup and Interpolate: EFFECTIVE ADDRESS MODE REGISTER REGISTER Dx SIZE MOTOROLA INSTRUCTION SET CPU32 4-160 REFERENCE MANUAL...
Page 209 Rounding mode field: The ’R’ bit controls rounding of the final result. When R = 0, the result is rounded according to the round-to-nearest algorithm. When R = 1, the result is returned unrounded. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 210 Not affected. Set if the most significant bit of the operand is currently set. Cleared otherwise. Set if the operand was zero. Cleared otherwise. Always cleared. Always cleared. Instruction Format: EFFECTIVE ADDRESS MODE REGISTER MOTOROLA INSTRUCTION SET CPU32 4-162 REFERENCE MANUAL...
Page 211 Reg. number: An , An) , PC) Reg. number: An — — , An, Xn) , PC, Xn) Reg. number: An — — (bd, An, Xn) Reg. number: An (bd, PC, Xn) — — CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-163...
Page 212 32. The range of vector operand values is 0–5, thus there are 16 possible vector numbers. Condition Codes: Not affected. Instruction Format: VECTOR Instruction Fields: Vector field — Specifies the trap vector to be taken. MOTOROLA INSTRUCTION SET CPU32 4-164 REFERENCE MANUAL...
Page 213 Condition field — The binary code for one of the conditions listed in the table. Opmode field — Selects the instruction form. 010 — Instruction is followed by word-size operand. 011 — Instruction is followed by long-word-size operand. 100 — Instruction has no operand. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-165...
Page 214 If the CCR overflow bit is set, there is a TRAPV exception (vector number 7). If the bit is not set, the processor performs no operation and execution continues with the next instruction. Condition Codes: Not affected. Instruction Format: MOTOROLA INSTRUCTION SET CPU32 4-166 REFERENCE MANUAL...
Page 215 Always cleared. Always cleared. Instruction Format: EFFECTIVE ADDRESS SIZE MODE REGISTER Instruction Fields: Size field — Specifies the size of the operation: 00 — Byte operation 01 — Word operation 10 — Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-167...
Page 216 Reg. number: An , An) , PC) Reg. number: An , An, Xn) , PC, Xn) Reg. number: An (bd, An, Xn) Reg. number: An (bd, PC, Xn) *Word or long word operation only MOTOROLA INSTRUCTION SET CPU32 4-168 REFERENCE MANUAL...
Page 217 Condition Codes: Not affected. Instruction Format: REGISTER Instruction Fields: Register field — Specifies the address register for the instruction. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-169...
Page 218: Instruction Format Summary
0011 Move Word 0100 Miscellaneous 0101 ADDQ/SUBQ/Scc/DBcc/TRAPcc 0110 Bcc/BSR/BRA 0111 MOVEQ 1000 OR/DIV/SBCD 1001 SUB/SUBX 1010 (Unassigned, Reserved) 1011 CMP/ EOR 1100 AND/MUL/ABCD/EXG 1101 ADD/ADDX 1110 Shift/Rotate/Bit Field 1111 Table Lookup and Interpolation MOTOROLA INSTRUCTION SET CPU32 4-170 REFERENCE MANUAL...
Page 219 Size Field: 00 = Byte 01 = Word 10 = Long CHK2 EFFECTIVE ADDRESS SIZE MODE REGISTER REGISTER Size Field: 00 = Byte 01 = Word 10 = Long BTST (Dynamic) EFFECTIVE ADDRESS REGISTER MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-171...
Page 220 WORD DATA (16 BITS) BYTE DATA (8 BITS) LONG DATA (32 BITS) Size Field: 00 = Byte 01 = Word 10 = Long ANDI to CCR BYTE DATA (8 BITS) ANDI to SR WORD DATA MOTOROLA INSTRUCTION SET CPU32 4-172 REFERENCE MANUAL...
Page 221 Bit Number Field: Modulo 32-bit selection BCHG (Static) EFFECTIVE ADDRESS MODE REGISTER BIT NUMBER Bit Number Field: Modulo 32-bit selection BCLR (Static) EFFECTIVE ADDRESS MODE REGISTER BIT NUMBER Bit Number Field: Modulo 32-bit selection CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-173...
Page 222 LONG DATA (32 BITS) Size Field: 00 = Byte 01 = Word 10 = Long MOVES EFFECTIVE ADDRESS SIZE MODE REGISTER REGISTER dr Field: 0 = EA to Register 1 = Register to EA MOTOROLA INSTRUCTION SET CPU32 4-174 REFERENCE MANUAL...
Page 223 Size Field: 00 = Byte 01 = Word 10 = Long MOVE from SR EFFECTIVE ADDRESS MODE REGISTER EFFECTIVE ADDRESS REGISTER SIZE MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long EFFECTIVE ADDRESS REGISTER MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-175...
Page 224 MOVE to CCR EFFECTIVE ADDRESS MODE REGISTER EFFECTIVE ADDRESS SIZE MODE REGISTER Size Field: 00 = Byte 01 = Word 10 = Long MOVE to SR EFFECTIVE ADDRESS MODE REGISTER NBCD EFFECTIVE ADDRESS MODE REGISTER MOTOROLA INSTRUCTION SET CPU32 4-176 REFERENCE MANUAL...
Page 225 Opmode Field: 010 = Extend Word 011 = Extend Long 111 = Extend Byte Long MOVEM EFFECTIVE ADDRESS SIZE MODE REGISTER REGISTER LIST MASK Size Field: 00 = Byte 01 = Word 10 = Long Register to EA Mask EA to Register Mask CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-177...
Page 226 Size Field: 0 = Long Word Product 1 = Quad Word Product MULS (Long) EFFECTIVE ADDRESS MODE REGISTER REGISTER Dq SIZE REGISTER Dr Size Field: 0 = Long Word Product 1 = Quad Word Product TRAP VECTOR MOTOROLA INSTRUCTION SET CPU32 4-178 REFERENCE MANUAL...
Page 227 DR Field: 0 = Move An to USP 1 = Move USP to An RESET STOP IMMEDIATE DATA Format/Offset Word (in stack frame) FORMAT VECTOR OFFSET Format Field: Four bits imply frame size; only values 000–0010 and 1000–1011 are used. DISPLACEMENT (16 BITS) CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-179...
Page 228 ADDQ EFFECTIVE ADDRESS DATA SIZE MODE REGISTER Data Field: Three bits of immediate data; 000–111 represent values of 1–7; 000 represents 8 Size Field: 00 = Byte 01 = Word 10 = Long MOTOROLA INSTRUCTION SET CPU32 4-180 REFERENCE MANUAL...
Page 229 32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF 8-BIT DISPLACEMENT 16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00 32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF 8-BIT DISPLACEMENT 16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00 32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-181...
Page 230 If R/M = 1, both registers must be address registers for Predecrement Addressing mode EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Opmode Field: Byte Word Long Operation 〉 〉 → 〉 (〈ea ) – (〈Dn 〈Dn 〉 〉 → 〉 (〈Dn ) – (〈ea 〈ea MOTOROLA INSTRUCTION SET CPU32 4-182 REFERENCE MANUAL...
Page 231 Opmode Field: Word Long Operation 〉 〉 → ) – (〈ea (〈An EFFECTIVE ADDRESS REGISTER OPMODE MODE REGISTER Opmode Field: Byte Word Long Operation 〉 〉 → 〉 (〈ea ) ⊕ (〈Dn 〈ea CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-183...
Page 232 REGISTER Ry Opmode Field: Specifies type of exchange 01000 — Data Register Exchange 01001 — Address Register Exchange 10001 — Data Register / Address Register (Rx specifies data register, Ry specifies address register) MOTOROLA INSTRUCTION SET CPU32 4-184 REFERENCE MANUAL...
Page 233 If I/R Field = 1, Specifies Data Register that contains Shift Count dr Field: 0 = Right 1 = Left Size Field: 00 = Byte 01 = Word 10 = Long I/R Field: 0 = Immediate Shift Count 1 = Register Shift Count CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL...
Page 234 I/R Field: 0 = Immediate Shift Count 1 = Register Shift Count ASL, ASR (Memory) EFFECTIVE ADDRESS MODE REGISTER dr Field: 0 = Right 1 = Left LSL, LSR (Memory) EFFECTIVE ADDRESS MODE REGISTER dr Field: 0 = Right 1 = Left MOTOROLA INSTRUCTION SET CPU32 4-186 REFERENCE MANUAL...
Page 235 REGISTER Dx SIZE REGISTER Dyn R Field: 0 = Unrounded 1 = Rounded TBLS, TBLSN (Lookup and Interpolate) EFFECTIVE ADDRESS MODE REGISTER REGISTER Dx SIZE R Field: 0 = Unrounded 1 = Rounded CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-187...
Page 236: Table Lookup And Interpolation Instructions
Figure 4-3 Table Example 1 The table consists of 257 word entries. As shown in Figure 4-3, the function is linear within the range 32768 ≤ X ≤ 49152. Table entries within this range are as follows: MOTOROLA INSTRUCTION SET CPU32 4-188 REFERENCE MANUAL...
Page 237: Table Example 2: Compressed Table
Using this information, the table instruction calculates dependent variable Y: Y = 1669 + (128 (1679 – 1669)) / 256 = 1674 4.6.2 Table Example 2: Compressed Table 1024 INDEPENDENT VARIABLE Figure 4-4 Table Example 2 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-189...
Page 238 Y = 1331 + (142 (1966 – 1311)) / 256 = 1674 The function chosen for Examples 1 and 2 is linear between data points. If another function had been used, interpolated values might not have been identical. MOTOROLA INSTRUCTION SET CPU32 4-190 REFERENCE MANUAL...
Page 239: Table Example 3: 8-Bit Independent Variable
17-entry table. X is passed to the subroutine, which returns an 8-bit result. The subroutine uses the following data, based on the function shown in Figure 4-5. (Subroutine) (Instruction) 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-191...
Page 240: Table Example 4: Maintaining Precision
The calculation is done once with the result of each TLI rounded before addition and once with only the final result rounded. Assume that the result of the three interpolations are as follows (a “.” indicates the binary radix point). MOTOROLA INSTRUCTION SET CPU32 4-192 REFERENCE MANUAL...
Page 241 〈ea〉, Dx TBLSN.B 〈ea〉, Dl TBLSN.B ADD.L Dx, Dm Long addition avoids problems with carry ADD.L Dm, Dl ASR.L#8, Move radix point BCC.B Fraction MSB in carry ADDQ.B #1, Dl L1: . . . CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4-193...
Page 242: Table Example 5: Surface Interpolations
4.8 Pipeline Synchronization with the NOP Instruction Although the no operation (NOP) instruction performs no visible operation, it does force synchronization of the instruction pipeline, since all previous instructions must complete execution before the NOP begins. MOTOROLA INSTRUCTION SET CPU32 4-194 REFERENCE MANUAL...
Page 243: State Transitions
SECTION 5 PROCESSING STATES This section describes the processing states of the CPU32. It includes a functional de- scription of the bits in the supervisor portion of the status register and an overview of actions taken by the processor in response to exception conditions.
Page 244: Supervisor Privilege Level
The RTE instruction causes a return to a program that was executing when an excep- tion occurred. When RTE is executed, the exception stack frame saved on the super- visor stack can be restored in either of two ways. MOTOROLA PROCESSING STATES CPU32 REFERENCE MANUAL...
Page 245: Address Spaces
During each bus cycle, the processor generates function code signals that permit se- lection of eight distinct 4-Gigabyte address spaces. Not all devices that incorporate the CPU32 support a full complement of memory. (Refer to the appropriate user's manual for details.) Selection varies according to the access required. Automatic selection of supervisor and user space, and of program and data space, is provided.
Page 246: Type 0000 — Breakpoint
T bit A1 designates the type of breakpoint. T = 0 indicates a software breakpoint; T = 1 indicates a hardware breakpoint. 5.3.1.2 Type 0001 — MMU Access This type of access is not supported by the CPU32 processor. This space is reserved for future use. 5.3.1.3 Type 0010 — Coprocessor Access This type of access is not supported by the CPU32 processor.
Page 247: Type 1111 — Interrupt Acknowledge
A[7:0] are used as 1 of 256 module register addresses. 5.3.1.5 Type 1111 — Interrupt Acknowledge Interrupt acknowledge is a CPU space type used for interrupt acknowledge. A[4:1] in- dicate the encoded interrupt level being acknowledged. LEVEL CPU32 PROCESSING STATES MOTOROLA REFERENCE MANUAL...
Page 248 MOTOROLA PROCESSING STATES CPU32 REFERENCE MANUAL...
Page 249: Definition Of Exception Processing
When initialization is complete, there are no fixed assignments. Since the VBR stores the vector table base address, the table can be located anywhere in memory. It can also be dynamically relocated for each task exe- cuted by an operating system. CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
Page 250: Exception Vector Assignments
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause excep- tions during normal execution. Illegal instructions, instruction fetches from odd ad- dresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions. MOTOROLA EXCEPTION PROCESSING CPU32 REFERENCE MANUAL...
Page 251: Exception Processing Sequence
M68000 Family processor, format 0000 is al- ways legal and always indicates that only the first four words of a frame are present. See 6.4 CPU32 Stack Frames for a complete discussion of exception stack frames. CPU32...
Page 252: Multiple Exceptions
6.1.3 Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode. When the CPU32 completes exception processing, it is ready to begin either exception processing for a pending exception, or execution of a handler routine. Priority assign- ment governs the order in which exception processing occurs, not the order in which exception handlers are executed.
Page 253: Processing Of Specific Exceptions
Execution of the RESET instruction does not cause a reset exception nor does it affect any internal CPU register, but it does cause the CPU32 to assert the RESET signal, resetting all internal and external peripherals.
Page 254: Bus Error
3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Bus error exception processing begins when the processor attempts to use informa- tion from an aborted bus cycle. MOTOROLA EXCEPTION PROCESSING CPU32 REFERENCE MANUAL...
Page 255: Address Error
No exception occurs if the branch is not taken. In this case, the fault address and return program counter value placed in the exception stack frame are the odd address, and the current instruction program counter points to the instruc- tion that caused the exception. CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
Page 256: Instruction Traps
Since the VBR on the CPU32 allows relocation of exception vectors, the exception vector ad- dress is not a reliable indication of a breakpoint. CPU32 breakpoint support is provided by extending the function of a set of illegal instructions ($4848–$484F).
Page 257: Format Error
An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal CPU32 instruction, if it is a MOVEC instruction that contains an undefined register specification field in the first extension word, or if it contains an indexed addressing mode extension word with bits [5:4] = 00 or bits [3:0] ≠...
Page 258: Privilege Violations
All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 Family members. Those customers requiring the use of an unimplemented opcode for synthesis of “custom instructions,” operating system calls, etc., should use this opcode.
Page 259: Tracing
To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on changes in pro- gram flow. In trace mode, a trace exception is generated after each instruction exe- cutes, allowing a debugging program to monitor the execution of a program under test.
Page 260: Interrupts
— all interrupt requests must be held asserted until they are acknowledged by the CPU. If the priority of the interrupt is greater than the current priority level, excep- tion processing begins. MOTOROLA EXCEPTION PROCESSING CPU32 6-12 REFERENCE MANUAL...
Page 261: Return From Exception
See 6.4 CPU32 Stack Frames for a description of stack frames. For a normal four-word frame, the processor updates the status register and program counter with data pulled from the stack, increments the supervisor stack pointer by eight, and resumes normal instruction execution.
Page 262: Fault Recovery
Rerun write cycle after RTE Faulted cycle was read-modify-write Instruction/other Read/write of faulted bus cycle Original operand size was long word Remaining size of faulted bus cycle FUNC Function code of faulted bus cycle MOTOROLA EXCEPTION PROCESSING CPU32 6-14 REFERENCE MANUAL...
Page 263 — SIZ will indicate original (and remaining) size. LG is set if the original was a long word — SIZ will indicate the remaining size at the time of fault. CPU32 EXCEPTION PROCESSING MOTOROLA...
Page 264: Types Of Faults
6.3.1 Types of Faults An efficient implementation of instruction restart dictates that faults on some bus cy- cles be treated differently than faults on other bus cycles. The CPU32 defines four fault types: released write faults, faults during exception processing, faults during MOVEM operand transfer, and faults on any other bus cycle.
Page 265: Type Ii: Prefetch, Operand, Rmw, And Movep Faults
Since postincremented registers are not updated until the end of an instruction, the register retains its preinstruction value unless overwritten by operand movement. The SSW for faults in this category contains the following bit pattern: CPU32 EXCEPTION PROCESSING MOTOROLA...
Page 266: Type Iv: Faults During Exception Processing
The second is to rerun the bus cycle via RTE. Type II fault handlers must terminate with RTE, but specific requirements must also be met before an instruction is restarted. MOTOROLA EXCEPTION PROCESSING CPU32 6-18 REFERENCE MANUAL...
Page 267: Type I) Completing Released Writes Via Software
Because the CPU32 has a 16-bit internal data bus, long operands require two bus ac- cesses. A fault during the second access of a long operand causes the LG bit in the SSW to be set.
Page 268: Type Iii) Correcting Faults Via Software
However, these memory locations are accessed a second time when the instruction is restarted. If a register used in an effective address calculation is overwritten before a fault occurs, an incorrect effective address is calculated upon instruction restart. MOTOROLA EXCEPTION PROCESSING CPU32 6-20 REFERENCE MANUAL...
Page 269: Type Iii) Correcting Faults Via Rte
6.4 CPU32 Stack Frames The CPU32 generates three different stack frames — the normal four- and six-word frames, and the twelve-word BERR stack frame. CPU32...
Page 270: Normal Four-Word Stack Frame
The address to which RTE returns is the address of the next instruction to be executed 6.4.3 BERR Stack Frame This stack frame is created when a bus cycle fault is detected. The CPU32 BERR stack frame differs significantly from the equivalent stack frames of other M68000 Family members.
Page 271: Internal Transfer Count Register
SP + $10 and the SSW is located at SP + $12). The fault address of a dynamically sized bus cycle is the address of the upper byte, regardless of the byte that caused the error. CPU32 EXCEPTION PROCESSING MOTOROLA...
Page 272: Format $C — Berr Stack For Prefetches And Operands
FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY) FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY) +$14 INTERNAL TRANSFER COUNT REGISTER +$16 SPECIAL STATUS WORD Figure 6-8 Format $C — Four- and Six-Word BERR Stack MOTOROLA EXCEPTION PROCESSING CPU32 6-24 REFERENCE MANUAL...
Page 273: Cpu32 Integrated Development Support
7.1.1 Background Debug Mode (BDM) Overview Microprocessor systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode. BDM incorporates a full set of debug options — registers can be viewed and/or altered, memory can be read or written, and test features can be invoked.
Page 274: Deterministic Opcode Tracking Overview
Figure 7-2 Bus State Analyzer Configuration 7.1.2 Deterministic Opcode Tracking Overview CPU32 function code outputs are augmented by two supplementary signals that mon- itor the instruction pipeline. The instruction fetch (IFETCH) output identifies bus cycles in which data is loaded into the pipeline, and signals pipeline flushes. The instruction pipe (IPIPE) output indicates when each mid-instruction pipeline advance occurs and when instruction execution begins.
Page 275: On-Chip Hardware Breakpoint Overview
BDM can be initiated in several ways — by externally generated breakpoints, by inter- nal peripheral breakpoints, by the background (BGND) instruction, or by catastrophic exception conditions. While in BDM, the CPU32 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated, high- speed, SPI-type serial command interface.
Page 276: Enabling Bdm
7.2.1 Enabling BDM Accidentally entering BDM in a non-development environment could lock up the CPU32 since the serial command interface would probably not be available. For this reason, BDM is enabled during reset via the breakpoint (BKPT) signal. BDM operation is enabled when BKPT is asserted (low), at the rising edge of RESET.
Page 277: Double Bus Fault
7.2.2.3 Double Bus Fault The CPU32 normally treats a double bus fault, or two bus faults in succession, as a catastrophic system error, and halts. When this condition occurs during initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected.
Page 278: Background Mode Registers
READ RESULTS/NEW COMMAND • LOAD COMMAND REGISTER • ENABLE SHIFT CLOCK • SHIFT IN/OUT 17 BITS • DISABLE SHIFT CLOCK • READ RESULT REGISTER IF RESULTS = "NOT READY" CONTINUE Figure 7-4 BDM Command Execution Flowchart MOTOROLA DEVELOPMENT SUPPORT CPU32 REFERENCE MANUAL...
Page 279: Current Instruction Program Counter (Pcc)
DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the oper- ating frequency of the target processor. Operable frequency range of the serial clock is from DC to one-half the processor system clock frequency.
Page 280: Cpu Serial Logic
FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Motorola reserves the right to use this bit for future enhancements. 7.2.7.1 CPU Serial Logic CPU serial logic, shown in the left-hand portion of Figure 7-5, consists of transmit and receive shift registers and of control logic that includes synchronization, serial clock generation circuitry, and a received bit counter.
Page 281: Serial Interface Timing Diagram
CLKOUT. At the falling edge of CLKOUT, the sampled value is made available to internal logic. If there is no synchronization between CPU32 and development system hardware, the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT.
Page 282: Development System Serial Logic
Another method is to assert BKPT, then continue to assert it until the CPU32 responds by asserting FREEZE. This method is useful for forcing a transi- tion into BDM when the bus is not being monitored. Each of these methods requires a slightly different serial logic design to avoid spurious serial clocks.
Page 283: Command Set
Figure 7-9 BKPT/DSCLK Logic Diagram BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first DSCLK. DSCLK is the gated serial clock. Normally high, it pulses low for each bit to be trans- ferred.
Page 284: Command Sequence Diagram
The CPU returns a “not ready” response unless the received command was decoded as unimplemented, in which case the response data is the il- legal command encoding. If an illegal command response occurs, the development system should retransmit the command. MOTOROLA DEVELOPMENT SUPPORT CPU32 7-12 REFERENCE MANUAL...
Page 285: Command-Sequence-Diagram Example
OR ADDRESS ERROR OCCURS ON SEQUENCE TAKEN IF MEMORY ACCESS ILLEGAL COMMAND IS RECEIVED BY CPU HIGH- AND LOW-ORDER RESULTS FROM PREVIOUS COMMAND 16 BITS OF RESULT RESPONSES FROM THE CPU Figure 7-10 Command-Sequence-Diagram Example CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7-13...
Page 286: Command Set Summary
Asserts RESET for 512 clock cycles. The CPU is not reset by this command. Synonymous with the CPU RESET instruction. No Operation NOP performs no operation and may be used as a null command. MOTOROLA DEVELOPMENT SUPPORT CPU32 7-14 REFERENCE MANUAL...
Page 287: Read A/D Register (Rareg/Rdreg)
Operand Data: Long-word data is written into the specified address or data register. The data is supplied most significant word first. Result Data: Command complete status ($0FFFF) is returned when register write is complete. CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7-15...
Page 288: Read System Register (Rsreg)
Operand data is written into the specified system control register. All registers that can be written in supervisor mode can be written in BDM. Several internal temporary reg- isters are also accessible. Command Format: MOTOROLA DEVELOPMENT SUPPORT CPU32 7-16 REFERENCE MANUAL...
Page 289: Read Memory Location (Read)
Read the sized data at the memory location specified by the long-word address. Only absolute addressing is supported. The SFC register determines the address space ac- cessed. Valid data sizes include byte, word, or long word. Command Format: OP SIZE Command Sequence: CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7-17...
Page 290: Write Memory Location (Write)
Write the operand data to the memory location specified by the long-word address. The destination function code (DFC) register determines the address space accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and long word. Command Format: OP SIZE Command Sequence: MOTOROLA DEVELOPMENT SUPPORT CPU32 7-18 REFERENCE MANUAL...
Page 291: Dump Memory Block (Dump)
The initial address is incremented by the operand size (1, 2, or 4) and saved in a tem- porary register. Subsequent DUMP commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. CPU32 DEVELOPMENT SUPPORT MOTOROLA...
Page 292 Word results return 16 bits of significant data; long-word results return 32 bits. Status of the read operation is returned as in the READ command: $0xxxx for success, $10001 for bus or address errors. MOTOROLA DEVELOPMENT SUPPORT CPU32 7-20 REFERENCE MANUAL...
Page 293: Fill Memory Block (Fill)
16 and 32 bits, respectively. Result Data: Status is returned as in the WRITE command: $0FFFF for a successful operation and $10001 for a bus or address error during write. CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL...
Page 294: Resume Execution (Go)
PC. BDM is exited, and nor- mal mode instruction execution begins. NOTE If a bus error or address error occurs during return address stacking, the CPU returns an error status via the serial interface and remains in BDM. MOTOROLA DEVELOPMENT SUPPORT CPU32 7-22 REFERENCE MANUAL...
Page 295 BDM and the CALL command can be used to patch the code as follows: 1. Breakpoint user program at CHKSTAT 2. Enter BDM 3. Execute CALL command to MISSING 4. Exit BDM 5. Execute MISSING code 6. Return to user program. CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7-23...
Page 296: Reset Peripherals (Rst)
NOP performs no operation and may be used as a null command where required. Command Format: Command Sequence: NEXT CMD "CMD COMPLETE" NEXT CMD "ILLEGAL" "NOT READY" Operand Data: None Result Data: The “command complete” response ($0FFFF) is returned during the next shift op- eration. MOTOROLA DEVELOPMENT SUPPORT CPU32 7-24 REFERENCE MANUAL...
Page 297: Future Commands
7.2.8.16 Future Commands Unassigned command opcodes are reserved by Motorola for future expansion. All un- used formats within any revision level will perform a NOP and return the ILLEGAL command response. 7.3 Deterministic Opcode Tracking The CPU32 utilizes deterministic opcode tracking to trace program execution. Two signals, IPIPE and IFETCH, provide all the information required to analyze the opera- tion of the instruction pipeline.
Page 298: Functional Model Of Instruction Pipeline
IRB (advance of IRA into IRB). Assertion for two clock cycles indi- cates that a new instruction has started (both IRA → IRB and IRB → IRC transfers MOTOROLA DEVELOPMENT SUPPORT CPU32 7-26 REFERENCE MANUAL...
Page 299: Opcode Tracking During Loop Mode
IPIPE continues to signal the start of instructions and the use of exten- sion words even though data is being recirculated internally. IFETCH returns to normal operation with the first fetch after exiting loop mode. CPU32 DEVELOPMENT SUPPORT MOTOROLA...
Page 300 MOTOROLA DEVELOPMENT SUPPORT CPU32 7-28 REFERENCE MANUAL...
Page 301: Resource Scheduling
8.1 Resource Scheduling The CPU32 contains several independently scheduled resources. The organization of these resources within the CPU32 is shown in Figure 8–1. Some variation in instruc- tion execution timing results from concurrent resource utilization. Because resource scheduling is not directly related to instruction boundaries, it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within which the instruction is executing.
Page 302: Instruction Pipeline
Figure 8–1 Block Diagram of Independent Resources 8.1.2 Instruction Pipeline The CPU32 contains a two-word instruction pipeline where instruction opcodes are decoded. Each stage of the pipeline is initially filled under microsequencer control and subsequently refilled by the prefetch controller as it empties.
Page 303: Prefetch Controller
If instruction prefetches, rather than operand accesses, were given priority, many instruction words would be flushed unused, and necessary oper- and cycles would be delayed. To maximize available bus bandwidth, the CPU32 will schedule a prefetch only when the next instruction is not a change-of-flow instruction, and when there is room in the pipeline for the prefetch.
Page 304: Instruction Execution Overlap
The following equation shows the method for calculating the overlap time: Overlap = min (Tail , Head INSTRUCTION A INSTRUCTION B INSTRUCTION C OVERLAP OVERLAP PERIOD PERIOD (ABSORBED BY (ABSORBED BY INSTRUCTION A) INSTRUCTION B) Figure 8–3 Attributed Instruction Times MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 REFERENCE MANUAL...
Page 305: Effects Of Wait States
8.1.5 Effects of Wait States The CPU32 access time for on-chip memory and peripherals is two clocks. While two- clock external accesses are possible when the bus is operated in a synchronous mode, a typical external memory speed is three or more clocks.
Page 306: Effects Of Negative Tails
8.1.7 Effects of Negative Tails When the CPU32 changes instruction flow, the instruction decode pipeline must begin refilling before instruction execution can resume. Refilling forces a two-clock idle peri- od at the end of the change of flow instruction.
Page 307: Instruction Stream Timing Examples
CONTROLLER FOR 2 FOR 2 EA FETCH ADDQ EA CALC INSTRUCTION MOVE A1,(AO)+ ADDQ TO <EA> <EA> CONTROLLER EXECUTION MOVE.W A1,(AO)+ CLR.W $30(A1) ADDQ.W #1,(AO) TIME Figure 8-4 Example 1 — Instruction Stream CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL...
Page 308: Timing Example 2: Branch Instructions
FETCH FOR 4 FOR 4 CONTROLLER OFFSET MOVE TO INSTRUCTION MOVEQ (A0) CALC TAKEN CONTROLLER MOVEQ EXECUTION MOVE.L D1,(AO) BLE.B NOT TAKEN #7,D1 TIME D1,D0 Figure 8-6 Example 2 — Branch Not Taken MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 REFERENCE MANUAL...
Page 309: Timing Example 3: Negative Tails
BRA.WFARAWAY MOVE.LD1, D0 Although the CPU32 has a two-word instruction pipeline, internal delay causes mini- mum branch instruction time to be three bus cycles. The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus — on a slow- er bus, there is no extra time for the third word.
Page 310: Instruction Timing Tables
If there is no time in the head to perform a prefetch, due to a previous trailing write, then additional time to do the prefetches must be allotted in the middle of the instruction or after the tail. MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8-10 REFERENCE MANUAL...
Page 311 CHK2, CMP2, and DBcc) are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle. This does not apply to long offsets or displacements. CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL...
Page 312: Fetch Effective Address
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8-12 REFERENCE MANUAL...
Page 313: Calculate Effective Address
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA...
Page 314: Move Instruction
The numbers inside parenthe- ses (r/p/w) are included in the total clock cycle number. All timing data assumes two- clock reads and writes. MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8-14 REFERENCE MANUAL...
Page 315: Arithmetic/Logic Instructions
Footnotes indicate when to account for the appropriate effective address times. The total number of clock cycles is outside the parentheses. The numbers inside pa- rentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL...
Page 316 8.1.6 Instruction Execution Time Calculation. A save operation is not run for long word divide and multiply instructions when 〈FEA〉 = Dn, MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8-16 REFERENCE MANUAL...
Page 317: Immediate Arithmetic/Logic Instructions
For long bus cycles, add two clocks to the tail and to the number of cycles. ∗An # fetch effective address time must be added for this instruction: 〈FEA〉 +〈FEA〉 + 〈OPER〉. CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL...
Page 318: Binary-Coded Decimal And Extended Instructions
X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8-18 REFERENCE MANUAL...
Page 319: Shift/Rotate Instructions
2. Head and cycle times are calculated as follows: (count ≤ 63): max (3 + n+ mod (n + 1,2), 6). 3. Head and cycle times are calculated as follows: (count ≤ 8): max (2 + n+ mod (n,2), 6). d = Direction (left or right) Clocks Shift Counts CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8-19...
Page 320: Bit Manipulation Instructions
(F, −1, not taken) DBcc 6(0/2/0) (F, not −1, taken) −2 DBcc 10(0/2/0) DBcc (T, not taken) 6(0/1/0)∗ (F, −1, not taken) DBcc 8(0/1/0)∗ (F, not −1, taken) DBcc 10(0/0/0)∗ *In loop mode MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8-20 REFERENCE MANUAL...
Page 321: Control Instructions
No additional tables are needed to calculate total effective execution time for these in- structions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL...
Page 322: Save And Restore Operations
< = Maximum time is indicated — certain data or mode combinations execute faster. Y = If a bus error occurred during a write cycle, the cycle is rerun by the RTE. MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8-22 REFERENCE MANUAL...
Page 323 Appendix A summarizes the characteristics of the microprocessors in the M68000 Family. The M68000 user’s manual includes more detailed information about the MC68000 and MC68010 differences. MC68000 MC68010 CPU32 MC68020 Data Bus Size (Bits) 8, 16 8, 16, 32 Address Bus Size (Bits)
Page 324 Stack Pointers MC68000 USP, SSP MC68010 USP, SSP CPU32 USP, SSP MC68020 USP, SSP (MSP, ISP) Status Register Bits MC68000 T, S, I0/I1/I2, X/N/Z/V/C MC68010 T, S, I0/I1/I2, X/N/Z/V/C CPU32 T1/T0, S, I0/I1/I2, X/N/Z/V/C MC68020 T1/T0, S, M, I0/I1/I2, X/N/Z/V/C...
Page 325 Table A-1 M68000 instruction Set Extensions Mnemonic Description CPU32 M68020 ◊ ◊ Supports 32-Bit Displacement ◊ BFxxxx Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFO, BFINS, BFSET, BFTST) ◊ BGND Background Operation ◊ ◊ BKPT New Instruction Function ◊ ◊...
Page 326 Table A-2 M68000 Addressing Modes Mode Mnemonic MC68010/ CPU32 MC68020 MC68000 ◊ ◊ ◊ Register Direct ◊ ◊ ◊ Address Register Indirect (An) ◊ ◊ ◊ Address Register Indirect with (An)+ Postincrement ◊ ◊ ◊ Address Register Indirect with-(An) Predecrement Address Register Indirect with ◊...
Page 327 Structures, Other (Stacks and Queues) 3-15 Set 7-11 Types 2-3 Summary 7-14 Deterministic Opcode Tracking 7-2, 7-25 Enabling 7-4 Development Features, Standard 7-1 Entering 7-5 Development Support 7-1 Returning from 7-7 Development System Serial Logic 7-10 CPU32 INDEX MOTOROLA REFERENCE MANUAL...
Page 328 Type III via Software 6-20 Conditional Branch 4-10, 8-20 Type IV via Software 6-21 Data Movement 4-6, 8-14 Recovery 6-14 Exception Related 4-11, 8-21 Types of 6-16 Integer Arithmetic 4-7, 8-15 Type I, Released Write 6-16 Logic 4-8, 8-15 CPU32 INDEX MOTOROLA REFERENCE MANUAL...
Page 329 Overlap 8-4 –S– –P– Save and Restore Operation Timing 8-22 Serial Interface (BDM) 7-7 Pipeline Sync with the NOP Instruction 4-194 Shift and Rotate Instruction Timing 8-19 Prefetch Controller 8-3 Shift and Rotate Instructions 4-9 CPU32 INDEX MOTOROLA REFERENCE MANUAL...
Page 330 Execution Overlap 8-7 Negative Tails 8-9 Timing Tables 8-10 Arihmetic/Logic Instructions 8-15 Binary-Coded Decimal/Extended Instructions 8-18 Bit Manipulation Instructions 8-20 Calculate Effective Address (CEA) 8-13 Conditional Branch Instructions 8-20 Control Instructions 8-21 Exception-Related Instructions 8-21 CPU32 INDEX MOTOROLA REFERENCE MANUAL...

Motorola CPU32 Reference Manual

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