Background Mode Registers - Motorola CPU32 Reference Manual

7.2.5 Background Mode Registers

BDM processing uses three special purpose registers to keep track of program context
during development. A description of each follows.
7.2.5.1 Fault Address Register (FAR)
The FAR contains the address of the faulting bus cycle immediately following a bus or
address error. This address remains available until overwritten by a subsequent bus
cycle. Following a double bus fault, the FAR contains the address of the last bus cycle.
The address of the first fault (if there was one) is not visible to the user.
7.2.5.2 Return Program Counter (RPC)
The RPC points to the location where fetching will commence after transition from
background mode to normal mode. This register should be accessed to change the
flow of a program under development. Changing the RPC to an odd value will cause
an address error when normal mode prefetching begins.
CPU ACTIVITY
ENTER BDM
• ASSERT FREEZE SIGNAL
• WAIT FOR COMMAND
EXECUTE COMMAND
• LOAD: NOT READY/ RESPONSE
• PERFORM COMMAND
• STORE RESULTS
Figure 7-4 BDM Command Execution Flowchart
MOTOROLA
7-6
IF RESULTS =
"NOT READY"
?
NO
CONTINUE
DEVELOPMENT SUPPORT
DEVELOPMENT SYSTEM ACTIVITY
SEND INITIAL COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT OUT 17 BITS
• DISABLE SHIFT CLOCK
READ RESULTS/NEW COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT IN/OUT 17 BITS
• DISABLE SHIFT CLOCK
• READ RESULT REGISTER
YES
REFERENCE MANUAL
CPU32