Figure 7-11. Static Read Transaction With Three Wait States - Sharp LH79524 User Manual

External Memory Controller
In Timing B, three wait states are also illustrated. However, in this case, the three wait
states have been programmed by setting SWAITRDx to 0x2 and SWAITOENx to 0x1. In
this case, nOE does not become asserted at the same time as nCSx. Instead, nOE is
delayed by the number of HCLK periods enumerated by SWAITOENx, which in this case
is one, represented by time 'D1'. Then, instead of the nOE signal deasserting one
HCLK period later, it is extended two wait states because of the programmed value in
SWAITRDx. The result is the same delay of three HCLK periods, but achieved in a
different way to also delay assertion of nOE.
TIMING A
NOTES:
With Register Programming:
SWAITDENx = D = 0x0
SWAITRDx = E = 0x3
TIMING B
NOTES:
With Register Programming:
SWAITOENx = D = 0x1
SWAITRDx = E = 0x2
7-12
HCLK
A[23:0]
D[31:0]
nCSx
nOE
E0
D1
nCSx
nOE

Figure 7-11. Static Read Transaction with Three Wait States

VALID ADDRESS
VALID DATA
E1 E2
E0 E1
Version 1.0
LH79524/LH79525 User's Guide
C
DATA
LATCHED
E3
E2
LH79525-110