Table 10-7. Imsc Register; Table 10-8. Imsc Register Definitions; Interrupt Mask Set Or Clear Register (Imsc) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

10.2.2.3 Interrupt Mask Set or Clear Register (IMSC)

On a Read, this register gives the current value of the mask on the relevant interrupt. Writ-
ing 1 to the particular bit sets the mask, enabling the interrupt to be read. Writing 0 clears
the corresponding mask. All bits are cleared to 0 when reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6
5
4
3
2
1
0
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 10-8. IMSC Register Definitions

NAME
/// Reserved Reading returns 0. Write the reset value.
SSP Protocol Error mask
SSPPEM
1 = Master Mode Protocol Error condition interrupt enabled
0 = Master Mode Protocol Error condition interrupt is masked
External Codec Protocol Error mask
ECPEM
1 = Slave Mode Protocol Error condition interrupt enabled
0 = Slave Mode Protocol Error condition interrupt is masked
Transmit Underrun Error mask
TXUEM
1 = Tx Underrun condition interrupt enabled
0 = Tx Underrun condition interrupt is masked
Transmit FIFO Interrupt mask (From SSP IMSC:TXIM bit)
TXIM
1 = Tx FIFO half empty or less condition interrupt enabled
0 = Tx FIFO half empty or less condition interrupt is masked
Receive FIFO Interrupt mask (From SSP IMSC:RXIM bit)
RXIM
1 = Rx FIFO half full or more condition interrupt enabled
0 = Rx FIFO half full or more condition interrupt is masked
Receive Timeout Interrupt mask (From SSP IMSC:RTIM bit)
RTIM
1 = Rx FIFO not empty and no read prior to timeout period interrupt is enabled
0 = Rx FIFO not empty and no read prior to timeout period interrupt is masked
Receive Overrun Interrupt mask (From SSP IMSC:RORIM bit)
RORIM
1 = Rx FIFO written to while full condition interrupt is enabled
0 = Rx FIFO written to while full condition interrupt is masked

Table 10-7. IMSC Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RO RO
0xFFFC8000 + 0x008
DESCRIPTION
Version 1.0
2
I S Converter
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW
10-17