Clock Generation; Rcpc Power Modes; Table 9-1. Clock And Enable States For Different Power Modes - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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Reset, Clock, and Power Controller

9.2.2 Clock Generation

The RCPC generates the system clock, CPU clock, and on-chip peripheral clocks from the:
• 14.7456 MHz crystal (connected to the XTALIN input pin and XTALOUT output pin)
• 32.768 kHz crystal (connected to the XTAL32IN input pin and XTAL32OUT output pin)
• The internally generated PLL clock.
The PLL circuit multiplies the 14.7456 MHz crystal oscillator's output frequency by seven to
produce the 103.22 MHz PLL clock. The system clock and CPU clock are divided from the
PLL clock according to the value programmed in the SysClkPrescaler Register (see
Section 9.3.2.7). The system clock connected to the DMA is not active after the reset. To
activate the DMA system clock, program the AhbClkCtrl Register (see Section 9.3.2.10).
The RTC clock is generated from the 32.768 kHz crystal oscillator output. The 32.768 kHz
oscillator's output is divided by 32768 to produce the 1 Hz RTC clock. The UART clocks
are generated from the 14.7456 MHz crystal oscillator. To activate the RTC and UART
clocks, program the APBPeriphClkCtrl0 Register (see Section 9.3.2.8).
The SSP and LCD clocks are generated from the system clock frequency. These clocks
are dividable according to the values programmed in the SSPPrescaler and LCDPrescaler
Registers. To activate these clocks, program the APBPeriphClkCtrl1 Register (see
Section 9.3.2.9). Leave the reserved registers set to their default values.

9.2.3 RCPC Power Modes

The RCPC supports five Power Modes:
• Active mode
• Standby mode
• Sleep mode
• Stop1 mode
• Stop2 mode.
Table 9-1 shows which clock and enable states are ON and OFF for the various
Power Modes.
NOTE: Do not have the LH75400/01/10/11 SoC device enter Standby, Sleep, Stop1, or Stop2 Mode while
9-4

Table 9-1. Clock and Enable States for Different Power Modes

DEVICE
RTC oscillator (32.768 kHz)
Oscillator (14.7456 MHz)
PLL
System clock
CPU clock
data is being transmitted or received.
LH75400/01/10/11 (Preliminary) User's Guide
ACTIVE STANDBY SLEEP STOP1 STOP2
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
7/15/03
ON
ON
ON
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

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