Slave Mode Reception - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

10.1.4.2 Slave Mode Reception

During Slave Mode reception, the I
frame input (PB2/SSPFRM/I2SWS) and data (PB4/SSPRX/I2SRXD/UARTRX0/
UARTIRRX0) from the external CODEC. The slave mode clock received by the SSP
2
is the I
CTRL:CLKINV bit.
The received frame is converted to a pulse and sent to the SSP. This conversion
is accomplished by generating a pulse to the SSP for every edge detected on
PB2/SSPFRM/I2SWS. If WSDEL is 0, the pulse is delayed by one clock.
The data received by the I
and sent to the SSP on SSPRXD.
I2SCLKOUT
I2SFSSIN
(WSDEL = 0)
I2SFSSIN
(WSDEL = 1)
SSPFSSIN
S slave mode clock input, PB3/SSPCLK/I2SCLK, inverted as indicated by the
2
S converter from the external CODEC is delayed by one clock
SSP
(SLAVE)
SSPCLKIN
SSPFSSIN
SSPRXD
Figure 10-11. I
I2SRXD MSB1
SSPRXD
Figure 10-12. I
2
S converter receives its clock (PB3/SSPCLK/I2SCLK),
2
I S CONVERTER
(SLAVE)
I2SCLKIN
I2SFSSIN
I2SRXD
2
S Slave Mode Reception Block Diagram
14 13 12
MSB1 14 13
2
S Slave Mode Reception Timing Diagram
Version 1.0
I
EXTERNAL CODEC
(MASTER)
SCK
WS
SD
2 1 LSB1 LSB2
3 2 1 LSB1 LSB2
2
S Converter
LH79525-101
14 13
14
LH79525-102
10-9