Table 17-50. Cntlx Register; Table 17-51. Cntlx Fields; Dma Channel X Control Register (Cntlx) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

17.2.3.14 DMA Channel x Control Register (CNTLx)

This register allows configuring various functions for DMA Channels 1 through 6.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:16
15
14:8
7:6
5:4
3
2
1
0

Table 17-50. CNTLx Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
MAX
0 0 0 0 0
RW RW RW RW RW

Table 17-51. CNTLx Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Bus Error If a bus error occurs while DMA is accessing memory on the
AHB, the DMA controller immediately terminates the DMA transfer and
interrupts the processor by setting this bit.
BUS_ERR
1 = Bus error occurred
0 = No bus error
Max Packet Size Program with the maximum packet size, in units of 8
MAX
bytes (required for Mode 1 only).
/// Reserved Reading returns 0. Write the reset value.
ENDPOINT Endpoint Number Program the endpoint number into this field (0-3).
Interrupt Enable
INTEN
1 = Enable interrupt
0 = Disable interrupt
DMA Operation Mode See full description in Table 17-39.
DMA_MODE
1 = DMA Mode 1
0 = DMA Mode 0
Data Direction
DIRECTION
1 = IN endpoint
0 = OUT endpoint
DMA Enable
DMAEN
1 = Enable DMA
0 = Disable DMA
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RW RW RW RO
Channel 1 = 0xFFFF5000 + 0x204
Channel 2 = 0xFFFF5000 + 0x214
Channel 3 = 0xFFFF5000 + 0x224
Channel 4 = 0xFFFF5000 + 0x234
Channel 5 = 0xFFFF5000 + 0x244
Channel 6 = 0xFFFF5000 + 0x254
FUNCTION
Version 1.0
Universal Serial Bus Device
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
ENDPOINT
0 0 0 0 0
RO RW RW RW RW
17 16
0 0
RO RO
1 0
EN
0 0
RW RW
17-33