Table 11-14. Muxctl5 Register; Table 11-15. Muxctl5 Fields; Multiplexing Control 5 Register (Muxctl5) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

11.2.2.7 Multiplexing Control 5 Register (MUXCTL5)

The MUXCTL5 Register allows software to configure a number of LH79524/LH79525 pins.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 11-14. MUXCTL5 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
PA1 PA0
0 0 0 0 0
RW RW RW RW RW

Table 11-15. MUXCTL5 Fields

BIT NAME
31:16 /// Reserved Reading returns 0. Write the reset value.
PA1/INT3/UARTTX2/UARTIRTX2 Assignment
00 = PA1
15:14 PA1
01 = INT3
10 = UARTTX2
11 = UARTIRTX2
PA0/INT2/UARTRX2/UARTIRRX2 Assignment
00 = PA0
13:12 PA0
01 = INT2
10 = UARTRX2
11 = UARTIRRX2
PB7/INT1/UARTTX0/UARTIRTX0 Assignment
00 = PB7
11:10 PB7
01 = INT1
10 = UARTTX0
11 = UARTIRTX0
PB6/INT0/UARTRX0/UARTIRRX0 Assignment
00 = PB6
9:8 PB6
01 = INT0
10 = UARTRX0
11 = UARTIRRX0
PB5/SSPTX/UARTTX1/UARTIRTX1 Assignment
00 = PB5
7:6 PB5
01 = SSPTX
10 = UARTTX1
11 = UARTIRTX1
PB4/SSPRX/UARTRX1/UARTIRRX1 Assignment
00 = PB4
5:4 PB4
01 = SSPRX
10 = UARTRX1
11 = UARTIRRX1
PB3/SSPCLK Assignment
00 = PB3
3:2 PB3
01 = SSPCLK
10 = Reserved
11 = Reserved
PB2/SSPFRM Assignment
00 = PB2
1:0 PB2
01 = SSPFRM
10 = Reserved
11 = Reserved
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
PB7 PB6 PB5
0 0 0 0
RW RW RW RW
0xFFFE5000 + 0x20
DESCRIPTION
Version 1.0
I/O Configuration
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
PB4 PB3
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
PB2
0 0
RW RW
11-9