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TCSR1—Timer Control/Status Register 1
Bit
7
OVF
Initial value
0
Read/Write
R/(W)*
Reset or NMI
0
NMI request
1
Internal reset request
Prescaler Select
0
The TCNT counts frequency-
division clock pulses of the
ø based prescaler (PSM)
1
The TCNT counts frequency-
division clock pulses of the
ø SUB-based prescaler (PSS)
Timer Enable
0
TCNT is initialized to H'00 and halted
1
TCNT counts
Timer Mode Select
0
Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows
1
Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows
Overflow Flag
0
[Clearing conditions]
• Cleared when 0 is written to the TME bit (Only applies to WDT1)
• Cleared by reading TCSR when OVF = 1, then write 0 in OVF
1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
Note: * Only a 0 may be written to this bit to clear the flag.
TCSR1 register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
1066
6
5
WT/IT
TME
PSS
0
0
R/W
R/W
R/W
Clock Select 2 to 0
PSS
CKS2
0
1
Note: * An overflow period is the time interval between the start of
counting up from H'00 on the TCNT and the occurrence of a
TCNT overflow.
H'FFA2(W), H'FFA2(R)
4
3
2
RST/NMI
CKS2
0
0
0
R/W
R/W
CKS1 CKS0
Clock
0
0
0
ø/2
1
ø/64
1
0
ø/128
1
ø/512
1
0
0
ø/2048
1
ø/8192
1
0
ø/32768
1
ø/131072
øSUB/2
0
0
0
1
øSUB/4
1
0
øSUB/8
1
øSUB/16
1
0
0
øSUB/32
1
øSUB/64
1
0
øSUB/128
1
øSUB/256
WDT1
1
0
CKS1
CKS0
0
0
R/W
R/W
Overflow Period*
(where ø = 20 MHz)
(where ø SUB = 32.768 kHz)
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
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