Table 2-4 Clock Signals; Clock; Table 2-5 Phase Lock Loop Signals - Motorola DSP56305 User Manual

Signal/Connection Descriptions

Clock

2.4 CLOCK
Signal
Type
Name
EXTAL Input
XTAL Output
2.5 PHASE LOCK LOOP (PLL)
Signal
Type
Name
PCAP Input
CLKOUT Output
2-8

Table 2-4 Clock Signals

State
During
Reset
Input External Clock/Crystal Input—EXTAL interfaces the
internal crystal oscillator input to an external crystal or
an external clock.
Chip-driven Crystal Output—XTAL connects the internal crystal
oscillator output to an external crystal. If an external
clock is used, leave XTAL unconnected.

Table 2-5 Phase Lock Loop Signals

State During
Reset
Input PLL Capacitor—PCAP is an input connecting an
off-chip capacitor to the PLL filter. Connect one
capacitor terminal to PCAP and the other terminal to
V
CCP
If the PLL is not used, PCAP may be tied to V
GND, or left floating.
Chip-driven Clock Output—CLKOUT provides an output clock
synchronized to the internal core clock phase.
If the PLL is enabled and both the multiplication and
division factors equal one, then CLKOUT is also
synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half
the frequency of EXTAL.
DSP56305 User's Manual
Signal Description
Signal Description
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