Parity Coding Modes Register Configuration; Figure 14-2 Cfsr Configuration In The Cipher Modes - Motorola DSP56305 User Manual

Input
Data

Figure 14-2 CFSR Configuration in the Cipher Modes

14.3.2

Parity Coding Modes Register Configuration

Figure 14-3 shows how the control register contents relate to CFSR configuration in the
Parity Coding modes.
MOTOROLA
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Majority Mask
To
Stepping
Function
Feedback Tap
Feedfwd Tap
Bit Select
Mask Tap
DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
Feedback
Tap
8
Feedforward Tap
Majority Bit Select
0001 0001 0000 0100 0001 0000
0000 0000 1000 1000 0000 0000
0000 1000 0010 0010 0000 0000
0000 1000 0000 0000 0000 0000
CCOP Block Diagram
7 6 5 4 3 2 1 0
Output
Data
MAJ
Input
Data
'0'
AA1301
14-5