Table 14-4 Ccop Operation Modes; Table 14-5 Lrc Settings; Left-Right Connection Bit (Lrc)—Ccsr Bit 8; Halt On Zero Detect Bit (Hozd)—Ccsr Bit 9 - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
OPM[1:0]
00
01
10
11
14.4.4.4 Left-Right Connection bit (LRC)—CCSR Bit 8
The Left-Right Connection bit (LRC) determines whether the input data bit is connected
to the left or right end of the CFSRs, if enabled. The input data is connected to the left
end of the CFSR when LRC is cleared, and to the right end when LRC is set. In the Parity
Coding mode with concatenated CFSRs (OPM[1:0] equals 11) the first two CFSRs (if
enabled by INE[1:0] bits in CSFTB) are treated as one long CFSR, and thus the input data
is connected either to the left end of CFSRB (LRC cleared) or to the right end of CFSRA
(LRC set). LRC should only be changed when CCOP is in CCOP individual reset.
LRC
0
1
14.4.4.5 Halt On Zero Detect bit (HOZD)—CCSR Bit 9
The Halt On Zero Detect control bit (HOZD) bit, when set, halts CCOP processing if a
zero is detected by the Zero Detect function during the run phase. This bit is directly
related to the Zero Detect function, thus it is operational in the Parity Coding modes and
ignored in the Cipher modes. When HOZD is cleared, the Zero Detect function does not
affect processing, and Parity Coding processing terminates after the Run Counter
reaches zero (Note that the output phase is disabled in the Parity Coding modes). When
HOZD is set, Parity Coding processing terminates when any of the following are zero in
the run phase:
• the Run Counter
• the bits specified by the Bit Select register CBSRA in Parity Coding Mode using
one CFSR (OPM[1:0] = 10)
14-16

Table 14-4 CCOP Operation Modes

Mode of operation
Normal Cipher mode
Step-by-step Cipher mode
Parity Coding mode using one CFSR
Parity Coding mode using two concatenated

Table 14-5 LRC Settings

Connect Input Data to Left End of CFSR
Connect Input Data to Right End of CFSR
DSP56305 User's Manual
CFSRs
Description
MOTOROLA