Motorola DSP56305 User Manual page 653

expanded mode 4-6
external address bus 2-9
external bus control 2-9
external data bus 2-9
external memory expansion port 2-9
EXTEST instruction 11-9
F
FE bit 8-16
Frame Sync Length bits (FSL1–FSL0) 7-22
Frame Sync Polarity bit (FSP) 7-23
Frame Sync Relative Timing bit (FSR) 7-23
frame sync selection
ESSI 7-51
Framing Error Flag bit (FE) 8-16
frequency
operation 1-7
FSL1–FSL0 bits 7-22
FSP bit 7-23
FSR bit 7-23
functional groups 2-4
functional signal groups 2-3
G
Global Data Bus 1-13
GO Command bit (GO) 10-6
,
GPIO 1-15 2-37
Timers 2-4
GPIO (ESSI0, Port C) 5-3
GPIO (ESSI1, Port D) 5-4
GPIO (HI08, Port B) 5-3
GPIO (SCI, Port E) 5-4
GPIO (Timer) 5-4
GPIO functionality
on ESSI 7-53
Ground 2-7
PLL 2-7
H
hardware stack 1-10
,
HI08 1-16 2-3
(GPIO) 5-3
, , ,
HI32 2-4 2-5 2-18 2-19
HI-Z instruction 11-11
Host Inteface 2-3
,
Host Interface 1-16 2-4
PCI 2-4
PCI bus 2-5
MOTOROLA
, ,
2-12 2-13
, ,
2-18 2-19
DSP56305 User's Manual
universal bus 2-5
host port
configuration 2-18
usage considerations 2-18
I
IDCODE instruction 11-9
IDLE bit 8-15
Idle Line Flag bit (IDLE) 8-15
Idle Line Interrupt Enable bit (ILIE) 8-12
IF0 bit 7-35
IF1 bit 7-36
ILIE bit 8-12
IME bit 10-8
instruction cache 3-3
location 3-10
instruction set 1-7
internal buses 1-13
interrupt 1-10
ESSI 7-45
,
sources 4-11 4-12
interrupt and mode control 2-15
,
interrupt control 2-15 2-17
Interrupt Mode Enable bit (IME) 10-8
Interrupt Priority Register P (IPR—P) 4-17
INV bit 9-13
Inverter bit (INV) 9-13
IPR—P 4-17
J
Joint Test Action Group (JTAG) 11-3
, ,
JTAG 1-7 1-11 2-38
JTAG instructions
BYPASS instruction 11-12
CLAMP instruction 11-10
DEBUG_REQUEST instruction 11-11
ENABLE_ONCE instruction 11-11
EXTEST instruction 11-9
HI-Z instruction 11-11
IDCODE instruction 11-9
SAMPLE/PRELOAD instruction 11-9
JTAG/OnCE Interface signals
Debug Event signal (DE signal) 10-4
L
LA register 1-10
LC register 1-10
logic 1-7
F
,
2-17
Index-3