Philips LPC213 Series User Manual page 93

Philips Semiconductors
Volume 1
9.3.11 UART0 Transmit Enable Register (U0TER - 0xE000 C030)
LPC2131/2/4/6/8's U0TER enables implementation of software flow control. When
TXEn=1, UART0 transmitter will keep sending data as long as they are available. As soon
as TXEn becomes 0, UART0 transmittion will stop.
Table 86
Table 86:
Bit
6:0
7
9.4 Architecture
The architecture of the UART0 is shown below in the block diagram.
The VPB interface provides a communications link between the CPU or host and the
UART0.
The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input. The
UART0 RX Shift Register (U0RSR) accepts valid characters via RXD0. After a valid
character is assembled in the U0RSR, it is passed to the UART0 RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UART0 transmitter block, U0TX, accepts data written by the CPU or host and buffers
the data in the UART0 TX Holding Register FIFO (U0THR). The UART0 TX Shift Register
(U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the
serial output pin, TXD0.
The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by
the UART0 TX block. The U0BRG clock input source is the VPB clock (PCLK). The main
clock is divided down per the divisor specified in the U0DLL and U0DLM registers. This
divided down clock is a 16x oversample clock, NBAUDOUT.
The interrupt interface contains registers U0IER and U0IIR. The interrupt interface
receives several one clock wide enables from the U0TX and U0RX blocks.
Status information from the U0TX and U0RX is stored in the U0LSR. Control information
for the U0TX and U0RX is stored in the U0LCR.
User manual
describes how to use TXEn bit in order to achieve software flow control.
UART0 Transmit Enable Register (U0TER - address 0xE000 C030) bit description
Symbol Description
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
TXEN When this bit is 1, as it is after a Reset, data written to the THR is output
on the TXD pin as soon as any preceding data has been sent. If this bit
is cleared to 0 while a character is being sent, the transmission of that
character is completed, but no further characters are sent until this bit is
set again. In other words, a 0 in this bit blocks the transfer of characters
from the THR or TX FIFO into the transmit shift register. Software
implementing software-handshaking can clear this bit when it receives
an XOFF character (DC3). Software can set this bit again when it
receives an XON (DC1) character.
Rev. 01 — 24 June 2005
UM10120
Chapter 9: UART0
Reset
value
NA
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
93