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Philips Semiconductors
Volume 1
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the I2CONCLR register.
Table 105: I2C0CONSET and I2C1CONSET used to configure Master mode
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I
2
I
condition is transmitted, the SI bit is set, and the status code in the I2STAT register is
0x08. This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by
writing a 1 to the SIC bit in the I2CONCLR register.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in
11.5.2 Master Receiver mode
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and the
data direction bit to the I
the data direction bit (R/W) should be 1 to indicate a read.
User manual
Bit
7
6
Symbol
-
I2EN
Value
-
1
2
C interface will enter master transmitter mode when software sets the STA bit. The
C logic will send the START condition as soon as the bus is free. After the START
Table 120
to
S
SLAVE ADDRESS
From Master to Slave
From Slave to Master
Fig 21. Format in the Master Transmitter mode
2
Rev. 01 — 24 June 2005
5
4
STA
STO
0
0
Table
123.
RW
A
DATA
"0" - Write
"1" - Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START Condition
P = STOP Condition
C Data register (I2DAT), and then clear the SI bit. In this case,
UM10120
Chapter 11: I
3
2
1
SI
AA
-
0
0
-
A
DATA
Data Transferred
(n Bytes + Acknowledge)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
C interfaces
0
-
-
A/A
P
111
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