Philips LPC213 Series User Manual page 161

Philips Semiconductors
Volume 1
13.3.6 SPI format with CPOL = 1,CPHA = 0
Single and continuous transmission signal sequences for SPI format with CPOL=1,
CPHA=0 are shown in
SCK
SSEL
MOSI MSB
MISO MSB
Fig 41. SPI frame format with CPOL = 1 and CPHA = 0 (a) single and b) continuous transfer)
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW, which causes slave
data to be immediately transferred onto the MISO line of the master. Master's MOSI pin is
enabled.
One half period later, valid master data is transferred to the MOSI line. Now that both the
master and slave data have been set, the SCK master clock pin becomes LOW after one
further half SCK period. This means that data is captured on the falling edges and be
propagated on the rising edges of the SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSEL line is returned to its idle HIGH state one SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
User manual
Figure
SCK
SSEL
MSB
MOSI
MSB
MISO
a) Motorola SPI frame format (single transfer) with CPOL=1 and CPHA=0
LSB
LSB
4 to 16 bits
b) Motorola SPI frame format (continuous transfer) with CPOL=1 and CPHA=0
•
The CLK signal is forced HIGH
•
SSEL is forced HIGH
•
The transmit MOSI/MISO pad is in high impedance
Rev. 01 — 24 June 2005
41.
LSB
LSB Q
4 to 16 bits
MSB
Q MSB
UM10120
Chapter 13: SSP
LSB
LSB Q
4 to 16 bits
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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