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Philips Semiconductors
Volume 1
SDA
SCL
Staus
bus
2
Fig 26. I
C serial interface block diagram
User manual
ADDRESS REGISTER
INPUT
FILTER
OUTPUT
STAGE
BIT COUNTER/
ARBITRATION &
SYNC LOGIC
INPUT
FILTER
SERIAL CLOCK
OUTPUT
GENERATOR
STAGE
I2CONSET
CONTROL REGISTER & SCL DUTY
I2CONCLR
I2SCLH
I2SCLL
STATUS
DECODER
I2STAT
Rev. 01 — 24 June 2005
I2ADR
COMPARATOR
SHIFT REGISTER
8
TIMING &
CONTROL
LOGIC
CYCLE REGISTERS
STATUS
REGISTER
UM10120
2
Chapter 11: I
C interfaces
8
ACK
I2DAT
PCLK
Interrupt
16
8
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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