Philips LPC213 Series User Manual page 120

Philips Semiconductors
Volume 1
STO is the STOP flag. Setting this bit causes the I
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to "not addressed" slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is high, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line on the following
situations:
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (high level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
11.7.2 I
0xE001 C018 and I2C1, I2C1CONCLR - 0xE005 C018)
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 109: I
Bit Symbol
1:0 -
2
3
4
User manual
2
C Interrupt Flag. This bit is set when the I
1. The address in the Slave Address Register has been received.
2. The general call address has been received while the general call bit (GC) in I2ADR is
set.
3. A data byte has been received while the I
4. A data byte has been received while the I
1. A data byte has been received while the I
2. A data byte has been received while the I
2
C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR -
2
C interface. Writing a one to a bit of this register causes the
2
C Control Set register (I2CONCLR: I2C0, I2C0CONCLR - address 0xE001 C018
and I2C1, I2C1CONCLR - address 0xE005 C018) bit description
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
AAC Assert acknowledge Clear bit.
2
SIC I C interrupt Clear bit.
- Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 01 — 24 June 2005
2
C is in the master receiver mode.
2
C is in the addressed slave receiver mode
2
C is in the master receiver mode.
2
C is in the addressed slave receiver mode.
2
C control register to be cleared. Writing a zero has no effect.
UM10120
Chapter 11: I
2
C interface to transmit a STOP
2
C-bus. When the bus detects
2
C state changes. However, entering
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
C interfaces
Reset
value
NA
0
NA
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