Processor Bus Memory Map; Default Processor Memory Map; Table 4-1. Processor Default View Of The Memory Map - Motorola MVME2400 Series Installation And Use Manual

Programming Details

Processor Bus Memory Map

4

Default Processor Memory Map

Processor Address
Start
00000000
80000000
80020000
FEF80000
FEF90000
FEFF0000
FF000000
FFF00000
4-2
The processor memory map configuration is under the control of the PHB
and SMC portions of the Hawk ASIC. The Hawk adjusts system mapping
to suit a given application via programmable map decoder registers. At
system power-up or reset, a default processor memory map takes over.
The default processor memory map that is valid at power-up or reset
remains in effect until reprogrammed for specific applications. The table
below defines the entire default map ($00000000 to $FFFFFFFF).

Table 4-1. Processor Default View of the Memory Map

End
7FFFFFFF
8001FFFF
FEF7FFFF 2GB-16MB-640KB
FEF8FFFF
FEFEFFFF
FEFFFFFF
FFEFFFFF
FFFFFFFF
Note The first 1MB of Flash bank A (soldered Flash up to 8MB)
appears in this range after a reset if the rom_b_rv control bit in
the SMC's ROM B Base/Size register is cleared. If the rom_b_rv
control bit is set, this address range maps to Flash bank B
(socketed 1MB Flash).
For detailed processor memory maps, including suggested
CHRP- and PREP-compatible memory maps, refer to the
MVME2400 Series VME Processor Module Programmer's
Reference Guide.
Size
2GB
128KB
64KB
384KB
64KB
15MB
1MB Flash Bank A or Bank B (See Note)
Computer Group Literature Center Web Site
Definition
Not Mapped
PCI/ISA I/O Space
Not Mapped
SMC Registers
Not Mapped
PHB Registers
Not Mapped