Table 3-6. Ppc60X Originated Bandwidth Matrix - Motorola MVME2400 Series Installation And Use Manual

Functional Description
3
Transaction
64-bit Writes
64-bit Reads
32-bit Writes
32-bit Reads
64-bit Writes
64-bit Reads
32-bit Writes
32-bit Reads
64-bit Writes
64-bit Reads
32-bit Writes
32-bit Reads
64-bit Writes
64-bit Reads
32-bit Writes
32-bit Reads
64-bit Writes
64-bit Reads
32-bit Writes
32-bit Reads
3-10

Table 3-6. PPC60x Originated Bandwidth Matrix

First 2 First 4
Cache Lines Cache Lines
MBytes
Clks Clks
Sec
14 381 58
- - -
14 381 78
- - -
14 457 38
- - -
14 457 50
- - -
14 457 67
- - -
14 457 98
- - -
14 305 48
- - -
14 305 64
- - -
14 305 29
- - -
14 305 37
- - -
First 6
Cache Lines
MBytes MBytes
Clks
Sec Sec
184 108 148
- - -
137 148 108
- - -
337 68 282
- - -
256 92 209
- - -
191 127 151
- - -
131 182 105
- - -
178 88 145
- - -
133 120 107
- - -
294 49 261
- - -
231 65 197
- - -
Computer Group Literature Center Web Site
Continuous
Clock
Ratio
Clks/ MBytes
Line Sec
25 107 5:2
32.5 82
35 76
42.5 63
15 213 3:2
22.5 142
21 152
28.5 112
30 107 3:1
36 89
42 76
48 67
20 107 2:1
28 76
28 76
36 59
10 213 1:1
18 118
14 152
22 97