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Motorola MVME2300 Series Installation And Use Manual

Motorola MVME2300 Series Installation And Use Manual

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MVME2300 Series
VME Processor Module
Installation and Use
V2300A/IH4
June 2001 Edition

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  • Page 1 MVME2300 Series VME Processor Module Installation and Use V2300A/IH4 June 2001 Edition...
  • Page 2 © Copyright 2000, 2001 Motorola, Inc. All rights reserved. Printed in the United States of America. ® Motorola and the Motorola symbol are registered trademarks of Motorola, Inc. ® PowerPC is a registered trademark of International Business Machines. ® Windows NT is a registered trademark of Microsoft Corporation in the United States and/or other countries.
  • Page 3 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
  • Page 4 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
  • Page 5 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 6 It is possible that this publication may contain reference to or information about Motorola products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

  • Page 7: Table Of Contents

    Contents About This Manual Summary of Changes ....................xvi Overview of Contents ....................xvi Comments and Suggestions ..................xvii Conventions Used in This Manual................xviii Terminology ......................xviii CHAPTER 1 Preparation and Installation Introduction........................1-1 Description .........................1-1 MVME2300 Module...................1-2 PMCspan Expansion Mezzanine ................1-3 PCI Mezzanine Cards (PMCs)................1-4 VMEsystem Enclosure ..................1-4 System Console Terminal ...................1-4 Overview of Start-Up Procedures ................1-5...
  • Page 8 Applying Power......................2-1 Description......................... 2-2 Switches......................2-2 ABT (S1) ..................... 2-3 RST (S2)...................... 2-3 Status Indicators ....................2-4 BFL (DS1)....................2-4 CPU (DS2) ....................2-4 PMC (DS3)....................2-4 PMC (DS4)....................2-4 10BaseT/100BaseTX Port .................. 2-4 DEBUG Port....................... 2-5 PMC Slots......................2-6 PCI Mezzanine Card (PMC Slot 1).............
  • Page 9 Programmable Timers..................3-18 Interval Timers ..................3-19 16/32-Bit Timers..................3-19 CHAPTER 4 Programming Introduction........................4-1 Memory Maps ......................4-1 Processor Bus Memory Map................4-2 Default Processor Memory Map..............4-2 PCI Local Bus Memory Map................4-3 VMEbus Memory Map ..................4-3 Programming Considerations..................4-4 PCI Arbitration ....................4-4 Interrupt Handling....................4-6 DMA Channels ....................4-8 Sources of Reset....................4-8 Endian Issues ......................4-9 Processor/Memory Domain ...............4-10...
  • Page 10 PCI Mezzanine Card Connectors - J21 through J24 ........B-16 APPENDIX C Troubleshooting Solving Startup Problems ..................C-1 APPENDIX D Related Documentation Motorola Computer Group Documents ..............D-1 Manufacturers’ Documents ..................D-2 Related Specifications ....................D-5 Abbreviations, Acronyms, and Terms to Know .............GL-1...
  • Page 11 List of Figures Figure 1-1. MVME2300 Switches, LEDs, Headers, Connectors ......1-9 Figure 1-2. General-Purpose Software-Readable Header........1-11 Figure 1-3. Typical Single-width PMC Module Placement on MVME2300 ..1-14 Figure 1-4. PMCspan-002 Installation on an MVME2300 ........1-16 Figure 1-5. PMCspan-010 Installation onto a PMCspan-002/MVME2300 ....1-18 Figure 2-1.
  • Page 13 List of Tables Table 1-1. MVME2300 Models .................1-2 Table 1-2. PMCspan Models..................1-3 Table 1-3. Start-Up Overview..................1-5 Table 3-1. MVME2300 Features ................3-1 Table 3-2. Power Requirements .................3-5 Table 3-3. MPC 60x Bus to PCI Access Timing ............3-6 Table 3-4. PCI to ECC Memory Access Timing............3-6 Table 3-5.

  • Page 15: About This Manual

    About This Manual The MVME2300 Series VME Processor Module Installation and Use manual provides information to install and use your MVME2300 Series VME Processor Module (hereafter referred to as MVME2300 or module). The module is based on an MPC603 and/or MPC604R PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O.

  • Page 16: Summary Of Changes

    Summary of Changes This is the fourth revision of the MVME2300 Series VME Processor Module Installation and Use manual. It supersedes the December 2000 edition and incorporates the following updates. New Issue Changes Replaces Date December Addition of the 333 MHz product configurations.

  • Page 17: Comments And Suggestions

    Documentation, lists all documentation related to the MVME2300 VME processor module. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:...

  • Page 18: Conventions Used In This Manual

    Conventions Used in This Manual The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files.
  • Page 19 An asterisk (*) following a signal name for signals that are level significant denotes that the signal is true or valid when the signal is low. An asterisk (*) following a signal name for signals that are edge significant denotes that the actions initiated by that signal occur on high to low transition.

  • Page 21: Introduction

    1Preparation and Installation Introduction This chapter provides a description of the MVME2300 Series VME Processor Module along with instructions for preparing and installing the module. Unless otherwise specified, the designation MVME2300 or the Note term module or modules refers to all available models of the MVME2300 series VME processor Modules.

  • Page 22: Mvme2300 Module

    Preparation and Installation MVME2300 Module The MVME2300 module is a powerful, low-cost embedded VME controller and intelligent PMC carrier board. The module is currently available in the configurations shown in the following table. The MVME2300 includes support circuitry such as ECC DRAM, PROM/flash memory, and bridges to the Industry Standard Architecture (ISA) bus and the VMEbus.

  • Page 23: Pmcspan Expansion Mezzanine

    Description The MVME2300 interfaces to the VMEbus via the P1 and P2 connectors. It also draws +5V, +12V, and -12V power from the VMEbus backplane through these two connectors. The +3.3V power, used for the PCI bridge chip and possibly for the PMC mezzanine, is derived onboard from the +5V power. Support for two IEEE P1386.1 PCI mezzanine cards is provided via eight 64-pin SMT connectors.

  • Page 24: Pci Mezzanine Cards (Pmcs)

    Preparation and Installation PCI Mezzanine Cards (PMCs) The PMC slots on the MVME2300 board are IEEE P1386.1 compliant. P2 I/O-based PMCs that follow the PMC committee recommendation for PCI I/O when using the 5-row VME64 extension connector will be pin-out compatible with the MVME2300.

  • Page 25: Overview Of Start-Up Procedures

    Overview of Start-Up Procedures Overview of Start-Up Procedures The following table lists the things you will need to do before you can use this board, and tells where to find the information you need to perform each step. Be sure to read this entire chapter and read all Caution and Warning notes before beginning.
  • Page 26 Preparation and Installation Table 1-3. Start-Up Overview (Continued) What you need to do ... Refer to ... Power up the system. Installing the MVME2300 Hardware Status Indicators If any problems occur, refer to the section Diagnostic Tests in Chapter 5, PPCBug.

  • Page 27: Unpacking The Mvme2300 Hardware

    The MVME2300 provides software control over most options. By setting bits in control registers after installing the module, you can modify its configuration. The MVME2300 control registers are briefly described in Chapter 4, Programming, with additional information found in the MVME2300 Series VME Processor Module Programmer’s Reference Guide.
  • Page 28 Preparation and Installation Some options, however, are not software-programmable. Such options are controlled through manual installation or removal of header jumpers or interface modules on the module itself or associated modules. Figure 1-1 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME2300.

  • Page 29: Figure 1-1. Mvme2300 Switches, Leds, Headers, Connectors

    Preparing the MVME2300 Hardware MVME 2300 Figure 1-1. MVME2300 Switches, LEDs, Headers, Connectors...

  • Page 30: Setting The Flash Memory Bank A/Bank B Reset Vector Header (J15)

    Preparation and Installation Setting the Flash Memory Bank A/Bank B Reset Vector Header (J15) Bank B consists of 1MB of 8-bit flash memory in two 32-pin PLCC 8-bit sockets. Bank A consists of four 16-bit Smart Voltage SMT devices that can be populated with 8Mbit flash devices (4MB) or 4Mbit flash devices (2MB).

  • Page 31: Setting The General-Purpose Software-Readable Header (J17)

    Preparing the MVME2300 Hardware System Controller Disabled Automatic System System Controller Controller Setting the General-Purpose Software-Readable Header (J17) Header J17 provides eight readable jumpers. These jumpers can be read as a register at ISA I/O address $801 (hexadecimal). Bit 0 is associated with header pins 1 and 2;...

  • Page 32: Pmcs

    Preparation and Installation PMCs For a discussion of any configurable items on the PMCs, refer to the user’s manual for the particular PMCs. PMCspan You need to use an additional slot in the VME chassis for each PMCspan expansion module you plan to use. Before installing a PMCspan on the MVME2300, you must install the selected PMCs on the PMCspan.

  • Page 33: Installing The Mvme2300 Hardware

    PMCspan modules onto the MVME2300, installing the MVME2300 into a VME chassis, and connecting an optional system console terminal. Motorola strongly recommends that you use an antistatic wrist strap and a Use ESD conductive foam pad when installing or upgrading a system. Electronic components, such as disk drives, computer boards, and memory modules, can be extremely sensitive to Electro-Static Discharge (ESD).

  • Page 34: Figure 1-3. Typical Single-Width Pmc Module Placement On Mvme2300

    Preparation and Installation 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2.

  • Page 35: Installing The Primary Pmcspan

    Installing the MVME2300 Hardware 5. Slide the edge connector(s) of the PMC module into the front panel opening(s) from behind and place the PMC module on top of the module. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors for a single-width PMC (J11/J12/J13/J14 or J21/J22/J23/J24, all eight for a double-width PMC) on the module.

  • Page 36: Figure 1-4. Pmcspan-002 Installation On An Mvme2300

    Preparation and Installation 2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VMEmodule card cage. 3.

  • Page 37: Installing A Secondary Pmcspan

    Installing the MVME2300 Hardware 4. Attach the four standoffs to the module. For each standoff: – Insert the threaded end into the standoff hole at each corner of the VME processor module. – Thread the locking nuts onto the standoff tips. –...

  • Page 38: Figure 1-5. Pmcspan-010 Installation Onto A Pmcspan-002/Mvme2300

    Preparation and Installation 2065 9708 Figure 1-5. PMCspan-010 Installation onto a PMCspan-002/MVME2300 Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning 1-18 Computer Group Literature Center Web Site...

  • Page 39: Installing The Mvme2300 Module

    Installing the MVME2300 Hardware 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground while you are performing the installation procedure.
  • Page 40 Preparation and Installation Inserting or removing modules with power applied may result in damage to module components. Caution Avoid touching areas of integrated circuitry; static discharge can damage these circuits. Dangerous voltages, capable of causing death, are present in this equipment.

  • Page 41: Installation Considerations

    5. Secure the module (and PMCspans if used) in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions. Some VME backplanes (such as those used in Motorola modular Note chassis systems) have an auto-jumpering feature for automatic propagation of the IACK and BG signals.
  • Page 42 DRAM at base physical address $00000000, as programmed by the PPCBug firmware. This may be changed via software to any other base address. Refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide for more information.

  • Page 43: Introduction

    2Operating Instructions Introduction This chapter provides information about powering up an MVME2300 system, and a functional description of the switches, status indicators, and I/O ports on the front panels of the module and PMCspan. Applying Power After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system.

  • Page 44: Description

    Operating Instructions Power-up/reset initialization STARTUP Initialize devices on the MVME2300 INITIALIZATION module/system Power On Self Test diagnostics POST Firmware-configured boot mechanism, BOOTING if so configured. Default is no boot. Interactive, command-driven on-line PowerPC MONITOR debugger, when terminal connected. Description The front panel of the MVME2300 module is shown on a following page. Switches There are two switches ) and four LED (light-emitting diode)

  • Page 45: Abt (S1)

    Description ABT (S1) When activated by software, the Abort switch, , can generate an interrupt signal from the base board to the processor at a user- programmable level. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the module’s flash memory.

  • Page 46: Status Indicators

    Operating Instructions Status Indicators There are four LED (light-emitting diode) status MVME 2300x indicators located on the MVME2300 front panel: BFL, , and PMC2 PMC1 BFL (DS1) The yellow LED indicates board failure; it lights when the BRDFAIL* signal line is active. CPU (DS2) The green LED indicates CPU activity;...

  • Page 47: Debug Port

    Description DEBUG Port The RJ45 port labeled on the front panel of the MVME2300 DEBUG supplies the module’s serial communications interface, implemented via a UART PC16550 controller chip from National Semiconductor. It is asynchronous only. This serial port is configured for EIA-232-D DTE, as shown in Figure 2-1.

  • Page 48: Pmc Slots

    Operating Instructions PMC Slots Two openings located on the front panel provide I/O expansion by allowing access to one or two 4-port single-wide or one 8-port double- wide PCI Mezzanine Card (PMC), connected to the PMC connectors on the MVME2300. For pin assignments for the PMC connectors, refer to Appendix B, Connector Pin Assignments.

  • Page 49: Pmcspan

    PMCspan PMCspan A PMCspan front panel is pictured at the right. The front panel is the same for all PMCspan models. There are two PMC slots, labeled PCI MEZZANINE CARD which support either two single-wide PMCs or one double-wide PMC. The PMCspan board has two sets of three 32-bit connectors for PMC interface to secondary PCI bus and user-specific I/O.

  • Page 51: Introduction

    Detailed descriptions of other MVME2300 blocks, including programmable registers in the ASICs and peripheral chips, can be found in the MVME2300 Series VME Processor Module Programmer’s Reference Guide. You may refer to it for a functional description of the MVME2300 in greater depth.
  • Page 52 Functional Description Table 3-1. MVME2300 Features (Continued) Feature Description Status LEDs Four: Board fail (BFL), CPU, PMC (one for PMC slot 2, one for slot 1) Timers One 16-bit timer in W83C553 ISA bridge; four 32-bit timers in Raven (MPIC) device) Watchdog timer provided in SGS-Thomson M48T59 Interrupts Software interrupt handling via Raven (PCI-MPU bridge) and Winbond...

  • Page 53: General Description

    General Description General Description The MVME2300 is a VME processor module equipped with an MPC 603 or MPC604R microprocessor. The product offers many standard features desirable in a computer system—including Ethernet and debug ports, Boot ROM, flash memory, DRAM, and interface for two PCI Mezzanine Cards (PMCs), contained in a one-slot VME package.

  • Page 54: Figure 3-1. Mvme2300 Block Diagram

    Functional Description CLOCK DEBUG CONNECTOR GENERATOR DRAM 16/32/64/128MB FLASH PROCESSOR 3MB or 5MB MPC604R SYSTEM REGISTERS PHB & MPIC RAVEN ASIC MEMORY CONTROLLER FALCON CHIPSET 33MHz 32/64-BIT PCI LOCAL BUS VME BRIDGE W83C553 UNIVERSE ETHERNET DEC21140 RTC/NVRAM/WD BUFFERS MK48T59/559 PC16550 UART REGISTERS VME P2...

  • Page 55: Pci Bus Latency

    Block Diagram The MPC 603 is a 64-bit processor with 16KB on-chip caches (16KB data cache and 16KB instruction cache). The MPC604R is a 64-bit processor with 32KB on-chip caches (32KB data cache and 32KB instruction cache). The Raven bridge controller ASIC provides the bridge between the PowerPC microprocessor bus and the PCI local bus.

  • Page 56: Table 3-3. Mpc 60X Bus To Pci Access Timing

    Functional Description The following table shows the access timings for various types of transfers initiated by a 60X system bus master to PCI: Table 3-3. MPC 60x Bus to PCI Access Timing Access Type System Clock Periods Required For: Total Clocks 1st Beat 2nd Beat...

  • Page 57: Dram Memory

    TSOPII DRAM are used to provide 16/32/64/128M. When populated, these blocks appears as Block A and Block B to the Falcon chipset. Refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide for additional information and programming details. The block diagram for the memory interface is shown in the following...

  • Page 58: Dram Latency

    Functional Description Memory Controller Falcon Chipset ECC DRAM Buffers 16M to 128M FLASH Buffers Buffers 3M to 5M Figure 3-2. Memory Block Diagram DRAM Latency The ECC memory access latency times for 60ns, fast page DRAMs are shown in the following table. Table 3-5.

  • Page 59: Table 3-6. Mpc 60X Bus To Dram Access Timing Using 50Ns, Edo Devices

    Block Diagram Table 3-5. MPC 60x Bus to DRAM Access Timing using 60ns Page Devices Access Type Clock Periods Required for: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4-Beat Write after 4-Beat Write 10/6 (Quad-word aligned) 1-Beat Read after Idle 1-Beat Read after 1-Beat Read 1-Beat Write after Idle 1-Beat Write after 1-Beat Write...

  • Page 60: Flash Memory

    Functional Description Table 3-6. MPC 60x Bus to DRAM Access Timing Using 50ns, EDO Devices Access Type Clock Periods Required for: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4-Beat Write after Idle 4-Beat Write after 4-Beat Write (Quad-word aligned) 1-Beat Read after Idle 1-Beat Read after 1-Beat Read...

  • Page 61: Flash Latency

    Block Diagram and 2 for Bank A factory configuration, or between J15 pins 2 and 3 for Bank B. When the jumper is installed, the Falcon chipset maps 0xFFF00100 to the Bank B sockets. The onboard monitor/debugger, PPCBug, resides in the flash chips. PPCBug provides functionality for: Booting the system Initializing after a reset...

  • Page 62: Ethernet Interface

    Functional Description Table 3-7.PowerPC 60x Bus to Flash Access Timing for Bank B (16-bit Port) Access type Clock Periods Required for: Total Clocks 1st Beat Beat Beat Beat 1-Beat Read (1 byte) 1-Beat Write Ethernet Interface The MVME2300 module uses a DECchip 21140/21143 PCI Fast Ethernet LAN controller to implement an Ethernet interface that supports 10BaseT/100BaseTX connections, via an RJ45 connector on the front panel.

  • Page 63: Pci Mezzanine Card (Pmc) Interface

    PMC connectors. For detailed programming information, refer to the PCI bus descriptions in the MVME2300 Series VME Processor Module Programmer’s Reference Guide and to the user documentation for the PMC modules you intend to use.

  • Page 64: Pmc Slot 1 (Single-Width Pmc)

    Functional Description PMC Slot 1 (Single-Width PMC) PMC slot 1 has the following characteristics: PCI Mezzanine Card (PMC) Mezzanine Type S1B: Single width, standard depth (75mm x 150mm) Mezzanine Size with front panel J11 to J14 (32/64-Bit PCI with front and rear I/O) PMC Connectors = 5.0Vdc Signaling Voltage...

  • Page 65: Pmc Slots 1 And 2 (Double-Width Pmc)

    The Universe chip includes Universe Control and Status Registers (UCSRs) for interprocessor communications. It can provide the VMEbus system controller functions as well. For detailed programming information, refer to the Universe User’s Manual and to the discussions in the MVME2300 Series VME Processor Module Programmer's Reference Guide. 3-15...

  • Page 66: Asynchronous Debug Port

    The external signals are ESD protected. This serial port can support 19.2 KBaud I/O. For detailed programming information, refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide and to the vendor documentation for the UART device.

  • Page 67: Real-Time Clock/Nvram/Timer Function

    Block Diagram ISA bus arbitration for DMA devices ISA interrupt mapping for four PCI interrupts Interrupt controller functionality to support 14 ISA interrupts Edge/level control for ISA interrupts Seven independently programmable DMA channels One 16-bit timer Three interval counters/timers Accesses to the configuration space for the PIB controller are performed by way of the CONADD and CONDAT (Configuration Address and Data) registers in the Raven bridge controller ASIC.

  • Page 68: Pci Host Bridge

    There are four programmable map decoders for each direction to provide flexible address mappings between the MPC and the PCI Local Bus. Refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide for additional information and programming details. Interrupt Controller (MPIC) The Raven ASIC provides an MPIC Interrupt Controller to handle various interrupt sources.

  • Page 69: Interval Timers

    For information on programming these timers, refer to the data sheet for the W83C553 PIB controller and to the MVME2300 Series VME Processor Module Programmer’s Reference Guide.

  • Page 71: Introduction

    MVME2300. This includes a description of memory maps, control and status registers, PCI arbitration, interrupt handling, sources of reset, and big/little-endian issues. For additional programming information about the MVME2300, refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide, listed in Appendix D, Related Documentation.

  • Page 72: Processor Bus Memory Map

    Bank B (socketed 1MB flash). For detailed processor memory maps, including suggested CHRP- and PREP-compatible memory maps, refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide. Computer Group Literature Center Web Site...

  • Page 73: Pci Local Bus Memory Map

    For detailed PCI memory maps, including suggested CHRP- and PREP- compatible memory maps, refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide. VMEbus Memory Map The VMEbus is programmable.

  • Page 74: Programming Considerations

    The PIB supports flexible arbitration modes of fixed priority, rotating priority, and mixed priority, as appropriate in a given application. Details on PCI arbitration can be found in the MVME2300 Series VME Processor Module Programmer’s Reference Guide. Computer Group Literature Center Web Site...

  • Page 75: Figure 4-1. Vmebus Master Mapping

    Programming Considerations VMEBUS PROCESSOR PCI MEMORY ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 NOTE 1 PCI MEMORY SPACE VME A24 VME A16 NOTE 3 VME A24 VME A16 NOTE 1 VME A24 PCI/ISA MEMORY SPACE VME A16 VME A24 I/O SPACE VME A16 RESOURCES NOTES:...

  • Page 76: Interrupt Handling

    The PCI bus (interrupts from PCI devices) The ISA bus (interrupts from ISA devices) Figure 4-2 illustrates interrupt architecture on the MVME2300. For details on interrupt handling, refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide. Computer Group Literature Center Web Site...

  • Page 77: Figure 4-2. Mvme2300 Interrupt Architecture

    Programming Considerations INT_ Processor (8529 Pair) MCP_ RavenMPIC SERR_& PERR_ PCI Interrupts ISA Interrupts 11559.00 9609 Figure 4-2. MVME2300 Interrupt Architecture...

  • Page 78: Dma Channels

    Programming The MVME2300 routes the interrupts from the PMCs and PCI expansion slots as follows: PMC Slot 1 PMC Slot 2 PCIX Slot INTA# INTB# INTC# INTD# INTA# INTB# INTC# INTD# INTA# INTB# INTC# INTD# IRQ9 IRQ10 IRQ11 IRQ12 RavenMPIC DMA Channels The PIB supports seven DMA channels.

  • Page 79: Endian Issues

    System Software Reset and Local Software Reset. The following table shows which devices are affected by the various types of resets. For details on using resets, refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide. Table 4-3. Classes of Reset and Effectiveness...

  • Page 80: Processor/Memory Domain

    Programming Processor/Memory Domain The MCP 603 or MPC604R processor can operate in both big-endian and little-endian mode. However, it always treats the external processor/memory bus as big-endian by performing address rearrangement and reordering when running in little-endian mode. The MPC registers in the Raven MPU/PCI bus bridge controller ASIC and the Falcon memory controller chip set, as well as DRAM, flash, and system registers, always appear as big-endian.

  • Page 81: Vmebus Domain

    Programming Considerations Role of the Universe ASIC Because the PCI bus is little-endian while the VMEbus is big-endian, the Universe PCI/VME bus bridge ASIC performs byte swapping in both directions (from PCI to VMEbus and from VMEbus to PCI) to maintain address invariance, regardless of the mode of operation in the processor’s domain.

  • Page 83: Chapter 5 Ppcbug

    Documentation. PPCBug Basics The PowerPC debug firmware, PPCBug, is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation. PPCBug provides a high degree of functionality, user friendliness, portability, and ease of maintenance.
  • Page 84 PPCBug PPCBug includes commands for: Display and modification of memory Breakpoint and tracing capabilities A powerful assembler and disassembler useful for patching programs A self-test at power-up feature which verifies the integrity of the system PPCBug consists of three parts: A command-driven, user-interactive software debugger, described in the PPCBug Firmware Package User’s Manual.

  • Page 85: Memory Requirements

    MPU, Hardware, and Firmware Initialization Memory Requirements PPCBug requires a maximum of 512KB of read/write memory (DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF. PPCBug Implementation PPCBug is written largely in the C programming language, providing benefits of portability and maintainability.
  • Page 86 PPCBug 7. Calculates the external bus clock speed of the MPU. 8. Delays for 750 milliseconds. 9. Determines the CPU base board type. 10. Sizes the local read/write memory (DRAM). 11. Initializes the read/write memory controller. Sets base address of memory to $00000000.

  • Page 87: Using Ppcbug

    Using PPCBug 26. Verifies the configuration data that is resident in NVRAM, and displays a warning message if the verification failed. 27. Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verification fails.

  • Page 88: Debugger Commands

    PPCBug After the debugger executes the command, the prompt reappears. However, if the command causes execution of user target code (for example GO) then control may or may not return to the debugger, depending on what the user program does. For example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program.
  • Page 89 Using PPCBug Table 5-1. Debugger Commands (Continued) Command Description Block of Memory Fill Block of Memory Initialize Block of Memory Move Breakpoint Insert NOBR Breakpoint Delete Block of Memory Search Block of Memory Verify Concurrent Mode NOCM No Concurrent Mode CNFG Configure Board Information Block Checksum...
  • Page 90 PPCBug Table 5-1. Debugger Commands (Continued) Command Description IDLE Idle Master MPU I/O Control for Disk I/O Inquiry I/O Physical (Direct Disk Access) I/O Teach for Configuring Disk Controller Idle MPU Register Display Idle MPU Register Modify Idle MPU Register Set Load S-Records from Host Macro Define/Display NOMA...
  • Page 91 Using PPCBug Table 5-1. Debugger Commands (Continued) Command Description NOPA Printer Detach PBOOT Bootstrap Operating System Port Format NOPF Port Detach PFLASH Program Flash Memory Put RTC into Power Save Mode ROMboot Enable NORB ROMboot Disable Register Display REMOTE Remote RESET Cold/Warm Reset Read Loop...

  • Page 92: Diagnostic Tests

    PPCBug Although a command to allow the erasing and reprogramming of flash memory is available to you, keep in mind that reprogramming any portion of flash memory will erase everything currently contained in flash, Caution including the PPCBug debugger. Note, however, that both banks A and B of flash contain the PPCBug debugger.
  • Page 93 Using PPCBug Table 5-2. Diagnostic Test Groups (Continued) Test Group Description NCR 53C8xx SCSI-2 I/O Processor Tests* PAR8730x Parallel Interface (PC8730x) Test UART Serial Input/Output Tests PCIBUS PCI/PMC Generic Tests Local RAM Tests MK48Txx Timekeeping Tests Serial Communications Controller (Z85C230) Tests* VGA543x Video Diagnostics Tests* VME2...

  • Page 95: Overview

    6Modifying the Environment Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the module’s NVRAM, also known as Battery Backed-up RAM (BBRAM). The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters.

  • Page 96: Cnfg - Configure Board Information Block

    The Board Information Block is factory-configured before shipment. There is no need to modify block parameters unless the NVRAM is corrupted. Refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide, listed in Appendix D, Related Documentation, for the actual location and other information about the Board Information Block.

  • Page 97: Env - Set Environment

    Refer to the PPCBug Firmware Package User’s Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your MVME2300 Series VME Processor Module Programmer’s Reference Guide.
  • Page 98 Modifying the Environment Remote Start Method Switch [G/M/B/N] = B? The Remote Start Method Switch is used when the MVME2300 is cross-loaded from another VME-based CPU, to start execution of the cross-loaded program. Use the Global Control and Status Register to pass and start execution of the cross-loaded program.
  • Page 99 ENV – Set Environment Negate VMEbus SYSFAIL* Always [Y/N] = N? Negate the VMEbus SYSFAIL signal during board initialization. ∗ Negate the VMEbus SYSFAIL signal after successful ∗ completion or entrance into the bug command monitor. (Default) SCSI Bus Reset on Debugger Startup [Y/N] = N? Local SCSI bus is reset on debugger setup.
  • Page 100 Modifying the Environment NVRAM Bootlist (GEV.fw-boot-path) Boot at power-up only [Y/N] = N? Give boot priority to devices defined in the fw-boot-path GEV at power-up reset only. Give power-up boot priority to devices listed in the fw-boot- path GEV at any reset. (Default) NVRAM Bootlist (GEV.fw-boot-path) Boot Abort Delay = 5? The time in seconds that a boot from the NVRAM boot list will delay before starting the boot.
  • Page 101 ENV – Set Environment Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape controller modules currently supported by PPCBug. (Default = $00) Auto Boot Device LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape devices currently supported by PPCBug.
  • Page 102 Modifying the Environment ROM Boot at power-up only [Y/N] = Y? ROMboot is attempted at power-up only. (Default) ROMboot is attempted at any reset. ROM Boot Enable search of VMEbus [Y/N] = N? VMEbus address space, in addition to the usual areas of memory, will be searched for a ROMboot module.
  • Page 103 ENV – Set Environment Network Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of network controller modules currently supported by PPCBug. (Default = $00) Network Auto Boot Device LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of network controller modules currently supported by PPCBug.
  • Page 104 Modifying the Environment Memory Size Enable [Y/N] = Y? Memory will be sized for Self Test diagnostics. (Default) Memory will not be sized for Self Test diagnostics. Memory Size Starting Address = 00000000? The default Starting Address is $00000000. Memory Size Ending Address = 02000000? The default Ending Address is the calculated size of local memory.
  • Page 105 ENV – Set Environment ROM Next Access Length (0 - 15) = 0? The value programmed into the ROMNAL field (Memory Control Configuration Register 8: bits 28-31) to represent wait states in access time for nibble (or burst) mode ROM accesses. The lowest allowable ROMNAL setting is $0;...

  • Page 106: Configuring The Vmebus Interface

    ENV asks the following series of questions to set up the VMEbus interface for the MVME2300 modules. To perform this configuration, you should have a working knowledge of the Universe ASIC as described in your MVME2300 Series VME Processor Module Programmer’s Reference Guide. VME3PCI Master Master Enable [Y/N] = Y? Set up and enable the VMEbus Interface.
  • Page 107 ENV – Set Environment PCI Slave Image 0 Base Address Register = 00000000? The configured value is written into the LSI0_BS register of the Universe chip. PCI Slave Image 0 Bound Address Register = 00000000? The configured value is written into the LSI0_BD register of the Universe chip.
  • Page 108 Modifying the Environment PCI Slave Image 2 Translation Offset = D0000000? The configured value is written into the LSI2_TO register of the Universe chip. PCI Slave Image 3 Control = C0400000? The configured value is written into the LSI3_CTL register of the Universe chip.
  • Page 109 ENV – Set Environment VMEbus Slave Image 1 Control = 00000000? The configured value is written into the VSI1_CTL register of the Universe chip. VMEbus Slave Image 1 Base Address Register = 00000000? The configured value is written into the VSI1_BS register of the Universe chip.
  • Page 110 Modifying the Environment VMEbus Slave Image 3 Bound Address Register = 00000000? The configured value is written into the VSI3_BD register of the Universe chip. VMEbus Slave Image 3 Translation Offset = 00000000? The configured value is written into the VSI3_TO register of the Universe chip.

  • Page 111: Appendix A Specifications

    ASpecifications Specifications The following table lists the general specifications for the MVME2300 VME processor module. The subsequent sections detail cooling requirements and EMC regulatory compliance. A complete functional description of the MVME2300 boards appears in Chapter 3, Functional Description. Specifications for the optional PMCs can be found in the documentation for those modules.
  • Page 112 Specifications Table A-1. Specifications (Continued) Characteristics Specifications Physical dimensions Height Double-high VME board, 9.2 in. (233 mm) (base board only) Front panel width 0.8 in. (19.8 mm) Front panel height 10.3 in. (261.7 mm) Depth 6.3 in. (160 mm) PCI Mezzanine Card Address/Data A32/D32/D64, PMC PN1-4 connectors (PMC) slots...

  • Page 113: Cooling Requirements

    (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VMEsystem chassis. Twenty-five-watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration.

  • Page 114: Emc Regulatory Compliance

    Specifications EMC Regulatory Compliance The MVME2300 was tested in an EMC-compliant chassis and meets the requirements for Class B equipment. Compliance was achieved under the following conditions: Shielded cables on all external I/O ports Cable shields connected to chassis ground via metal shell connectors bonded to a conductive module front panel Conductive chassis rails connected to chassis ground.

  • Page 115: Introduction

    BConnector Pin Assignments Introduction This appendix summarizes the pin assignments for the following groups of interconnect signals for the MVME2300 Series VME Processor Module: Connector Location Table VMEbus connector Table B-1 VMEbus connector, P2 I/O Table B-2 Debug serial port, RJ45...

  • Page 116: Vmebus Connector - P1

    Connector Pin Assignments VMEbus Connector - P1 Two 160-pin DIN type connectors, P1 and P2, supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the IEEE P1014-1987 VMEbus Specification and the VME64 Extension Standard.

  • Page 117: Vmebus Connector - P2

    Pin Assignments Table B-1. P1 VMEbus Connector Pin Assignments (Continued) Not Used VIRQ6 VA13 Not Used ∗ VIRQ5 VA12 Not Used ∗ Not Used VIRQ4 VA11 Not Used ∗ VIRQ3 VA10 Not Used ∗ Not Used VIRQ2 Not Used ∗ VIRQ1 Not Used ∗...
  • Page 118 Connector Pin Assignments Table B-2. P2 Connector Pin Assignment (Continued) PMC2_23 (J24-23) PMC1_30 (J14-30) VD17 PMC1_29 (J14-29) PMC2_22 (J24-22) PMC1_32 (J14-32) VD18 PMC1_31 (J14-31) PMC2_24 (J24-24) PMC2_26 (J24-26) PMC1_34 (J14-34) VD19 PMC1_33 (J14-33) PMC2_25 (J24-25) PMC1_36 (J14-36) VD20 PMC1_35 (J14-35) PMC2_27 (J24-27) PMC2_29 (J24-29) PMC1_38 (J14-38)

  • Page 119: Serial Port Connector - Debug (J2

    Pin Assignments Serial Port Connector - DEBUG (J2) A standard RJ45 connector located on the front plate of the MVME2300 provides the interface to the asynchronous serial debug port. The pin assignments for this connector are as follows: Table B-3. DEBUG (J2) Connector Pin Assignments Ethernet Connector - 10BaseT/100BaseT (J3) The 10BaseT/100BaseTx connector is an RJ45 connector located on the front plate of the MVME2300.

  • Page 120: Cpu Debug Connector - J1

    Connector Pin Assignments CPU Debug Connector - J1 One 190-pin Mictor connector with center row of power and ground pins is used to provide access to the Processor Bus and some miscellaneous signals. The pin assignments for this connector are as follows: Table B-5.

  • Page 121: Table B-5. Debug Connector Pin Assignments

    Pin Assignments Table B-5. Debug Connector Pin Assignments (Continued) PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PA20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PD32 PD33 PD34 PD35 PD36 PD37...
  • Page 122 Connector Pin Assignments Table B-5. Debug Connector Pin Assignments (Continued) PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47 PD48 PD49 PA50 PD51 PD52 PD53 PD54 PD55 PD56 PD57 PD58 PD59 PD60 PD61 PD62 PD63 PDPAR0 PDPAR1 PDPAR2 PDPAR3 PDPAR4 PDPAR5 PDPAR6...
  • Page 123 Pin Assignments Table B-5. Debug Connector Pin Assignments (Continued) +3.3V TSIZ0 TSIZ1 TSIZ2 CSE0 GLOBAL# CSE1 SHARED# DBWO# AACK# ARTY# XATS# DRTY# TBST# TEA# DBG# DBB# ABB# TCLK_OUT CPUGNT0# CPUREQ0#...
  • Page 124 Connector Pin Assignments Table B-5. Debug Connector Pin Assignments (Continued) CPUREQ1# INT0# CPUGNT1# MCPI# INT1# SMI# MCPI1# CKSTPI# L2BR# CKSTPO# L2BG# HALTED L2CLAIM# TLBISYNC# TBEN SUSPEND# DRVMOD0 DRVMOD1 NAPRUN SRESET1# QREQ# SRESET0# QACK# HRESET# CPUCLK CPUCLK CPUCLK TRST# B-10 Computer Group Literature Center Web Site...

  • Page 125: Pci Expansion Connector - J18

    Pin Assignments PCI Expansion Connector - J18 One 114-pin Mictor connector with center row of power and ground pins is used to provide PCI/PMC expansion capability. The pin assignments for this connector are as follows: Table B-6. J18 - PCI Expansion Connector Pin Assignments +3.3V +3.3V PCICLK...
  • Page 126 Connector Pin Assignments Table B-6. J18 - PCI Expansion Connector Pin Assignments (Continued) PCIRST# C/BE1# C/BE0# C/BE3# C/BE2# AD11 AD10 AD13 AD12 AD15 AD14 AD17 AD16 AD19 AD18 AD21 AD20 AD23 AD22 AD25 AD24 AD27 AD26 AD29 AD28 AD31 AD30 B-12 Computer Group Literature Center Web Site...
  • Page 127 Pin Assignments Table B-6. J18 - PCI Expansion Connector Pin Assignments (Continued) PAR64 Reserved C/BE5# C/BE4# C/BE7# C/BE6# AD33 AD32 AD35 AD34 AD37 AD36 AD39 AD38 AD41 AD40 AD43 AD42 AD45 AD44 AD47 AD46 AD49 AD48 AD51 AD50 AD53 AD52 AD55 AD54 AD57...

  • Page 128: Pci Mezzanine Card Connectors - J11 Through J14

    Connector Pin Assignments PCI Mezzanine Card Connectors - J11 through J14 Four 64-pin SMT connectors, J11 through J14, supply 32/64-bit PCI interfaces and P2 I/O between the MVME2300 board and an optional add- on PCI Mezzanine Card (PMC) in PMC Slot 1. The pin assignments for PMC Slot 1 are listed in the following two tables.

  • Page 129: Table B-8. J13 - J14 Pmc1 Connector Pin Assignments

    Pin Assignments Table B-7. J11 - J12 PMC1 Connector Pin Assignments (Continued) AD09 AD08 +3.3V C/BE0# AD07 Not Used AD06 AD05 +3.3V Not Used AD04 Not Used +5V (Vio) AD03 Not Used Not Used AD02 AD01 Not Used AD00 ACK64# +3.3V REQ64# Not Used...

  • Page 130: Pci Mezzanine Card Connectors - J21 Through J24

    Connector Pin Assignments Table B-8. J13 - J14 PMC1 Connector Pin Assignments (Continued) +5V (Vio) AD44 PMC1_39 (P2-C20) PMC1_40 (P2-A20) AD43 AD42 PMC1_41 (P2-C21) PMC1_42 (P2-A21) AD41 PMC1_43 (P2-C22) PMC1_44 (P2-A22) AD40 PMC1_45 (P2-C23) PMC1_46 (P2-A23) AD39 AD38 PMC1_47 (P2-C24) PMC1_48 (P2-A24) AD37 PMC1_49 (P2-C25)

  • Page 131: Table B-9. J21 And J22 Pmc2 Connector Pin Assignments

    Pin Assignments Table B-9. J21 and J22 PMC2 Connector Pin Assignments (Continued) PMCREQ2# Not Used +5V (Vio) AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 +3.3V C/BE3# IDSEL2 AD23 AD22 AD21 +3.3V AD20 AD19 AD18 +5V (Vio) AD17 AD16 C/BE2# FRAME# Not Used IRDY#...
  • Page 132 Connector Pin Assignments Table B-10. J23 and J24 PMC2 Connector Pin Assignments Reserved PMC2_1 (P2-D1) PMC2_2 (P2-Z1) C/BE7# PMC2_3 (P2-D2) PMC2_4 (P2-D3) C/BE6# C/BE5# PMC2_5 (P2-Z3) PMC2_6 (P2-D4) C/BE4# PMC2_7 (P2-D5) PMC2_8 (P2-Z5) +5V (Vio) PAR64 PMC2_9 (P2-D6) PMC2_10 (P2-D7) AD63 AD62 PMC2_11 (P2-Z7)

  • Page 133: Table B-10. J23 And J24 Pmc2 Connector Pin Assignments

    Pin Assignments Table B-10. J23 and J24 PMC2 Connector Pin Assignments (Continued) +5V (Vio) AD32 Not Used Not Used Reserved Reserved Not Used Not Used Reserved Not Used Not Used Reserved Not Used Not Used B-19...

  • Page 135: Solving Startup Problems

    CTroubleshooting Solving Startup Problems In the event of difficulty with your MVME2300 VME Processor Module, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment.
  • Page 136 Troubleshooting Table C-1. Troubleshooting Problems (Continued) Condition Possible Problem Possible Resolution: II. There is a A. The keyboard Recheck the keyboard and/or mouse connections display on the or mouse may be and power. terminal, but input connected from the keyboard incorrectly.
  • Page 137 Solving Startup Problems Table C-1. Troubleshooting Problems (Continued) Condition Possible Problem Possible Resolution: IV. Debug prompt A. The initial 1. Start the onboard calendar clock and timer. Type: debugger set mmddyyhhmm <CR> PPC1-Bug> appears at environment where the characters indicate the month, day, year, powerup, but the parameters may be hour, and minute.
  • Page 138 Troubleshooting Table C-1. Troubleshooting Problems (Continued) Condition Possible Problem Possible Resolution: 6. You may need to use the cnfg command (see your board Debugger Manual) to change clock speed and/or Ethernet Address, and then later return to: env <CR> and step 3. 7.

  • Page 139: Motorola Computer Group Documents

    DRelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting MCG’s World Wide Web literature site,...

  • Page 140: Manufacturers' Documents

    Related Documentation Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets and user’s manuals. For your convenience, a source for the listed document is also provided. It is important to note that in many cases, the information shown is preliminary and the revision levels of the documents are subject to change without notice.
  • Page 141 Document Title and Source Number PowerPC 603 RISC Microprocessor Technical Summary MPC603E/D MPC604E/D PowerPC 604 RISC Microprocessor Technical Summary Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 PowerPC 603 RISC Microprocessor User’s Manual MPC603EUM/D MPC604EUM/AD PowerPC 604 RISC Microprocessor User’s Manual...
  • Page 142 Related Documentation Publication Document Title and Source Number 21140 Fast Etherworks PCI 10-Flash-100 Ethernet Adapter Owner’s EK-DE500-OM Manual Compaq Telephone: 1-800.at.compaq W83C553 Enhanced System I/O Controller with PCI Arbiter (PIB) W83C553F Winbond Electronics Corporation M48T59 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet M48T59 STMicroelectronics...

  • Page 143: Related Specifications

    Related Specifications Related Specifications For additional information, refer to the following table for related specifications. For your convenience, a source for the listed document is also provided. It is important to note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
  • Page 144 Third Edition, Version 1.0, Volumes I and II International Business Machines Corporation PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 Morgan Kaufmann Publishers, Inc.

  • Page 145: Abbreviations, Acronyms, And Terms To Know

    Glossary Abbreviations, Acronyms, and Terms to Know This glossary defines some of the abbreviations, acronyms, and key terms used in this document. An Ethernet implementation in which the physical medium is a 10Base-5 doubly shielded, 50-ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters (also referred to as thicknet).
  • Page 146 Glossary Attachment Unit Interface Battery Backed-up Random Access Memory BBRAM Having big-endian and little-endian byte ordering capability. bi-endian A byte-ordering method in memory where the address n of a word big-endian corresponds to the most significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most significant byte.
  • Page 147 The Green signals (G-Y) can be extracted by these two signals. Common Hardware Reference Platform (CHRP) A specification published by Apple, IBM, and Motorola which defines the devices, interfaces, and data formats that make up a CHRP-compliant system using a PowerPC processor.
  • Page 148 A local area network standard that uses radio frequency signals Ethernet carried by coaxial cables. The DRAM controller chip developed by Motorola for the Falcon MVME2600 and MVME3600 series of boards. It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144-bit ECC DRAM (system memory array) and/or ROM/Flash.
  • Page 149 Fiber Distributed Data Interface. A network based on the use of FDDI optical-fiber cable to transmit data in non-return-to-zero, invert-on- 1s (NRZI) format at speeds up to 100 Mbps. First-In, First-Out. A memory that can temporarily hold data so that FIFO the sending device can send data faster than the receiving device can accept it.
  • Page 150 (left to right) 3, 2, 1, 0, with 3 being the most significant byte. MBLT Multiplexed BLock Transfer Micro Channel Architecture MCA (bus) Motorola Computer Group Modified Frequency Modulation Musical Instrument Digital Interface. The standard format for MIDI recording, storing, and playing digital music. Multimedia Personal Computer...
  • Page 151 The PowerPC-to-PCI bus bridge chip developed by Motorola for the MPC105 Ultra 603/Ultra 604 system board. It provides the necessary interface between the MPC603/MPC604 processor and the Boot ROM (secondary cache), the DRAM (system memory array), and the PCI bus.
  • Page 152 Glossary Operating System. The software that manages the computer resources, accesses files, and dispatches programs. One-Time Programmable The range of colors available on the screen, not necessarily palette simultaneously. For VGA, this is either 16 or 256 simultaneous colors out of 262,144. A connector that can exchange data with an I/O device eight bits at parallel port a time.
  • Page 153 Instructions can be sent simultaneously to three types of independent execution units (branch units, fixed-point units, and floating-point units), where they can execute concurrently, but finish out of order. PowerPC is used by Motorola, Inc. under license from IBM. The first implementation of the PowerPC family of PowerPC 601™...
  • Page 154 All data in RAM is lost when the computer is turned off. Row Address Strobe. A clock signal used in dynamic RAMs to control the input of the row addresses. The PowerPC-to-PCI local bus bridge chip developed by Motorola Raven for the MVME2600 and MVME3600 series of boards. It provides the necessary interface between the PowerPC 60x bus and the PCI bus, and acts as interrupt controller.
  • Page 155 TV receiver. See 10base-5. thick Ethernet See 10base-2. thin Ethernet See 10Base-T. twisted-pair Ethernet Universal Asynchronous Receiver/Transmitter UART ASIC developed by Tundra in consultation with Motorola, that Universe provides the complete interface between the PCI bus and the 64-bit VMEbus. GL-11...
  • Page 156 When data is copied from disk to main memory, the physical address is changed to the virtual address. See VESA Local bus (VL bus). VL bus MCG second generation VMEbus interface ASIC (Motorola) VMEchip2 MCG ASIC that interfaces between the PCI bus and the VMEchip2 VME2PCI device.
  • Page 157 EXtended Graphics Array. An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels. Luminance. This determines the brightness of each spot (pixel) on a Y Signal CRT screen either color or B/W systems, but not the color. GL-13...
  • Page 159 Index board layout, MVME2300 Numerics board placement 1-20 10/100 BASET port board structure 16/32-bit timers 3-19 board won’t autoboot bridge controller functions 3-16 abbreviations, acronyms, and terms to know buses, standard 3-3, GL-1 abort (interrupt) signal cables, I/O ports ABT switch (S1) chapter listing (see also appendix listing) address pipelining 3-9, 3-10...
  • Page 160 Index debug console terminal Falcon memory controller chip set 4-2, 4-6, debug firmware, PPCBug 4-10 DEBUG port 1-21 features, hardware DEBUG port, MVME2300 features, Universe ASIC 3-15 debug prompt gone firmware initialization debugger firmware, PPCBug commands flash latency 3-11 directory 5-10 flash memory 1-10, 3-10...
  • Page 161 multiple MVME2300 boards 1-22 LEDs, MVME2300 front panel MVME2300 1-19 literature web site MVME2300 hardware 1-13 local reset (LRST) MVME2300 into chassis 1-19 lowercase 5-11 PCI mezzanine cards 1-13 PMC carrier board 1-18 manufacturers’ documents PMC module 1-14 memory available PMCs 1-13 memory block diagram...
  • Page 162 Index ordering literature asynchronous 3-16 overview of manual debug 3-16 Ethernet power needs 1-3, 1-21 P1 and P2 connectors 1-3, 1-21, power requirements 3-5, A-1, parallel port PowerPC bus to DRAM access timing 3-6, parity 1-12, PC16550 PPC1-Bug> 5-10 PCI bus 3-3, 3-13, 4-3, PPC1-Diag>...
  • Page 163 RF emissions terminal has no display, display not on termi- ROMboot enable 6-7, 6-11 terminal setup 1-21 terminal won’t respond to keyboard/mouse SCSI bus SD command 5-10 testing the hardware 5-10 secondary PMCspan installation 1-17 timekeeper device sending your comments xvii timeout, global 1-22...
  • Page 164 Index VMEbus system controller selection (J16) VMEsystem enclosure Winbond PCI/ISA bus bridge controller 3-16, IN-6 Computer Group Literature Center Web Site...

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