Table of Contents
Advertisement
Board Level Hardware Description
1
Table 1-5. Local I/O Devices Memory Map (Continued)
Address Range
$FFFBD000 - $FFFBFFFF
$FFFC0000 - $FFFCFFFF
$FFFD0000 - $FFFEFFFF
Notes
1. For a complete description of the register bits, refer to the data sheet for the specific chip.
For a more detailed memory map, refer to the MVME162LX Embedded Controller
Programmer's Reference Guide.
2. The SCC is an 8-bit device located on an MC2chip private data bus. Byte access is required.
3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate
with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR
may be 8, 16 or 32 bits. Byte reads should be used to read the interrupt vector.
4. This area does not return an acknowledge signal. If the local bus timer is enabled, the
access times out and is terminated by a TEA signal.
5. Size is approximate.
6. Port commands to the 82596CA must be written as two 16-bit writes: upper word first and
lower word second.
7. Not used.
8. To use this area, the ECC mezzanine board must be installed. If it is not installed, no
acknowledge signal is returned; if the local bus timer is enabled, the access times out and
is terminated by a TEA signal.
9. Repeats on 8KB boundaries.
1-32
Devices Accessed
Reserved
M48T58 (BBRAM, TOD Clock)
Reserved
Port
Size
Notes
Width
- -
12KB
4
D32-D8
64KB
1, 9
- -
128KB
4
Advertisement
Table of Contents
