Table 1-4. Local Bus Memory Map - Motorola 700 Series Installation And Use Manual

Board Level Hardware Description
1
Address Range
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
$FF800000-$FF9FFFFF
$FFA00000-$FFBFFFFF
$FFC00000-$FFDFFFFF
$FFE00000-$FFE1FFFF
1-28
I/O space must be marked cache inhibit and serialized in its page
table. Table 1-5 on page 1-30 further defines the map for the local
I/O devices.

Table 1-4. Local Bus Memory Map

Devices
Accessed
DRAM on parity
mezzanine
DRAM on ECC
mezzanine
Onboard SRAM
VMEbus
A32/A24
IP_a memory
IP_b memory
Flash/EPROM
EPROM/Flash
Not decoded
Onboard SRAM
default
Port
Size
Width
D32 4MB-16MB
D32 4MB-32MB
D32 128KB
D32-D16 --
D32-D8 64KB-8MB
D32-D8 64KB-8MB
D32 2MB
D32 2MB
D32 2MB
D32 128KB
Software
Cache Notes
Inhibit
N 2
N 2
N 2
? 4
? 2, 4
? 2, 4
N 1, 5
N 5
N
N