Uart0 Fifo Control Register; 0Xe000 C008); Uart0 Line Control Register; 0Xe000 C00C) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
initialization conditions implement a one character delay minus the stop bit whenever
THRE=1 and there have not been at least two characters in the U0THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART0 THR FIFO has held two or more characters at one time and
currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
9.3.8 UART0 FIFO Control Register (U0FCR - 0xE000 C008)
The U0FCR controls the operation of the UART0 Rx and TX FIFOs.
Table 91:
Bit
0
1
2
5:3
7:6
9.3.9 UART0 Line Control Register (U0LCR - 0xE000 C00C)
The U0LCR determines the format of the data character that is to be transmitted or
received.
Table 92: UART0 Line Control Register (U0LCR - address 0xE000 C00C) bit description
Bit Symbol
1:0 Word Length
Select

User manual

UART0 FIFO Control Register (U0FCR - address 0xE000 C008) bit description
Symbol Value
FIFO Enable 0
1
RX FIFO 0
Reset
1
TX FIFO 0
Reset
1
- 0
RX Trigger
Level
00
01
10
11
Value Description
00 5 bit character length
01 6 bit character length
10 7 bit character length
11 8 bit character length
Rev. 01 — 12 January 2006
Description
UART0 FIFOs are disabled. Must not be used in the
application.
Active HIGH enable for both UART0 Rx and TX
FIFOs and U0FCR[7:1] access. This bit must be set
for proper UART0 operation. Any transition on this
bit will automatically clear the UART0 FIFOs.
No impact on either of UART0 FIFOs.
Writing a logic 1 to U0FCR[1] will clear all bytes in
UART0 Rx FIFO and reset the pointer logic. This bit
is self-clearing.
No impact on either of UART0 FIFOs.
Writing a logic 1 to U0FCR[2] will clear all bytes in
UART0 TX FIFO and reset the pointer logic. This bit
is self-clearing.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
These two bits determine how many receiver
UART0 FIFO characters must be written before an
interrupt is activated.
trigger level 0 (1 character or 0x01).
trigger level 1 (4 characters or 0x04).
trigger level 2 (8 characters or 0x08).
trigger level 3 (14 characters or 0x0E).
UM10161
Chapter 9: UART0
Reset value
0
0
0
NA
0
Reset value
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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