User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 150:SSP Data Register (SSPDR - address
0xE006 8008) bit description . . . . . . . . . . . . .177
Table 151:SSP Status Register (SSPDR - address
0xE006 800C) bit description . . . . . . . . . . . .177
Table 152:SSP Clock Prescale Register (SSPCPSR -
address 0xE006 8010) bit description . . . . . .177
Table 153:SSP Interrupt Mask Set/Clear register (SSPIMSC
- address 0xE006 8014) bit description . . . . .178
Table 154:SSP Raw Interrupt Status register (SSPRIS -
address 0xE006 8018) bit description . . . . . .178
Table 155:SSP Masked Interrupt Status register (SSPMIS
-address 0xE006 801C) bit description . . . . .179
Table 156:SSP interrupt Clear Register (SSPICR - address
0xE006 8020) bit description . . . . . . . . . . . . .179
Table 157:ADC pin description . . . . . . . . . . . . . . . . . . . .180
Table 158:ADC registers . . . . . . . . . . . . . . . . . . . . . . . . .181
Table 159:A/D Control Register (AD0CR - address
0xE003 4000 ) bit description . . . . . . . . . . . .182
Table 160:A/D Global Data Register (AD0GDR - address
0xE003 4004 ) bit description . . . . . . . . . . . .183
Table 161:A/D Status Register (ADSTAT, ADC0: AD0STAT -
address 0xE003 4004 and ADC1: AD1STAT -
address 0xE006 0004) bit description . . . . . .184
Table 162:A/D Status Register (ADSTAT, ADC0: AD0STAT -
address 0xE003 4004 ) bit description . . . . .184
Table 163:A/D Data Registers (ADDR0 to ADDR7, ADC0:
AD0DR0 to AD0DR7) bit description. . . . . . .185
Table 164:Timer/Counter pin description . . . . . . . . . . . .188
Table 165:TIMER/COUNTER0 and TIMER/COUNTER1
register map . . . . . . . . . . . . . . . . . . . . . . . . . .189
Table 166:Interrupt Register (IR, TIMER0: T0IR - address
0xE000 4000 and TIMER1: T1IR - address
0xE000 8000) bit description . . . . . . . . . . . . .190
Table 167:Timer Control Register (TCR, TIMER0: T0TCR -
address 0xE000 4004 and TIMER1: T1TCR -
address 0xE000 8004) bit description . . . . . .191
Table 168:Count Control Register (CTCR, TIMER0:
T0CTCR - address 0xE000 4070 and TIMER1:
T1TCR - address 0xE000 8070) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Table 169:Match Control Register (MCR, TIMER0: T0MCR -
address 0xE000 4014 and TIMER1: T1MCR -
address 0xE000 8014) bit description . . . . . .193
Table 170:Capture Control Register (CCR, TIMER0: T0CCR
- address 0xE000 4028 and TIMER1: T1CCR -
address 0xE000 8028) bit description . . . . . .194
Table 171:External Match Register (EMR, TIMER0: T0EMR
- address 0xE000 403C and TIMER1: T1EMR -
address0xE000 803C) bit description . . . . . .195
Table 172:External match control . . . . . . . . . . . . . . . . . .196
Table 173:PWM Control Register (PWMCON, TIMER0:

User manual

PWM0CON - 0xE000 4074 and TIMER1:
PWM1CON - 0xE000 8074) bit description . . 196
Table 174:Timer/Counter pin description . . . . . . . . . . . . 201
Table 175:TIMER/COUNTER2 and TIMER/CT3OUNTER3
register map . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 176:Interrupt Register (IR, TIMER2T2: T2IR - address
0xE007 0000 and TIMER3: T3IR - address
0xE007 4000) bit description . . . . . . . . . . . . . 203
Table 177:Timer Control Register (TCR, TIMER2: T2TCR -
address 0xE007 0004 and TIMER3: T3TCR -
address 0xE007 4004) bit description. . . . . . 204
Table 178:Count Control Register (CTCR, TIMER2:
T2CTCR - address 0xE007 0070 and TIMER3:
T3TCR - address 0xE007 4070) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 179:Match Control Register (MCR, TIMER2: T2MCR -
address 0xE007 0014 and TIMER3: T3MCR -
address 0xE007 4014) bit description. . . . . . 206
Table 180:Capture Control Register (CCR, TIMER2: T2CCR
- address 0xE007 0028 and TIMER3: T3CCR -
address 0xE007 4028) bit description. . . . . . 207
Table 181:External Match Register (EMR, TIMER2: T2EMR
- address 0xE007 003C and TIMER3: T3EMR -
address0xE007 4016-bit3C) bit description . 208
Table 182:External match control . . . . . . . . . . . . . . . . . . 208
Table 183:PWM Control Register (PWMCON, TIMER0:
PWM0CON - 0xE007 0074 and TIMER1:
PWM1CON - 0xE007 4074) bit description . . 209
Table 184:Real Time Clock (RTC) register map . . . . . . . 214
Table 185:Miscellaneous registers . . . . . . . . . . . . . . . . . 215
Table 186:Interrupt Location Register (ILR - address
0xE002 4000) bit description . . . . . . . . . . . . 216
Table 187:Clock Tick Counter Register (CTC - address
0xE002 4004) bit description . . . . . . . . . . . . 216
Table 188:Clock Control Register (CCR - address
0xE002 4008) bit description . . . . . . . . . . . . 216
Table 189:Counter Increment Interrupt Register (CIIR -
address 0xE002 400C) bit description . . . . . 217
Table 190:Alarm Mask Register (AMR - address
0xE002 4010) bit description . . . . . . . . . . . . 217
Table 191:Consolidated Time register 0 (CTIME0 - address
0xE002 4014) bit description . . . . . . . . . . . . 218
Table 192:Consolidated Time register 1 (CTIME1 - address
0xE002 4018) bit description . . . . . . . . . . . . 218
Table 193:Consolidated Time register 2 (CTIME2 - address
0xE002 401C) bit description . . . . . . . . . . . . 218
Table 194:Time counter relationships and values. . . . . . 219
Table 195:Time counter registers . . . . . . . . . . . . . . . . . . 219
Table 196:Alarm registers. . . . . . . . . . . . . . . . . . . . . . . . 220
Table 197:Reference clock divider registers . . . . . . . . . . 221
Table 198:Prescaler Integer register (PREINT - address
Rev. 01 — 12 January 2006
UM10161
Chapter 22: Supplementary information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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