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Volume 1
Table 67:
Fast GPIO port 0 Direction register (FIO0DIR - address 0x3FFF C000) bit description
Bit
Symbol
Value Description
31:0
FP0xDIR
0
1
Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table
registers allow easier and faster access to the physical port pins.
Table 68:
Fast GPIO port 0 Direction control byte and half-word accessible register description
Register
Register
name
length (bits)
& access
FIO0DIR0
8 (byte)
FIO0DIR1
8 (byte)
FIO0DIR2
8 (byte)
FIO0DIR3
8 (byte)
FIO0DIRL
16
(half-word)
FIO0DIRU
16
(half-word)
8.4.2 Fast GPIO port 0 Mask register (FIOMASK, Port 0: FIO0MASK -
0x3FFF C010)
This register is available in the enhanced group of registers only. It is used to select the
port's pins that will and will not be affected by a write accesses to the FIOPIN, FIOSET or
FIOCLR register. The mask register also filters out the port's content when the FIOPIN
register is read.
A zero in this register's bit enables an access to the corresponding physical pin via a read
or write access. If a bit in this register is one, the corresponding pin will not be changed
with write access and if read, will not be reflected in the updated FIOPIN register. For
software examples, see
Table 69:
Fast GPIO port 0 Mask register (FIO0MASK - address 0x3FFF C010) bit description
Bit
Symbol
Value Description
31:0
FP0xMASK
0
1
User manual
Fast GPIO Direction control bits. Bit 0 in FIO0DIR controls P0.0 ... Bit 30 in
FIO0DIR controls P0.30.
Controlled pin is input.
Controlled pin is output.
68. Next to providing the same functions as the FIODIR register, these additional
Address
Description
0x3FFF C000
Fast GPIO Port 0 Direction control register 0. Bit 0 in FIO0DIR0
register corresponds to P0.0 ... bit 7 to P0.7.
0x3FFF C001
Fast GPIO Port 0 Direction control register 1. Bit 0 in FIO0DIR1
register corresponds to P0.8 ... bit 7 to P0.15.
0x3FFF C002
Fast GPIO Port 0 Direction control register 2. Bit 0 in FIO0DIR2
register corresponds to P0.16 ... bit 7 to P0.23.
0x3FFF C003
Fast GPIO Port 0 Direction control register 3. Bit 0 in FIO0DIR3
register corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C000
Fast GPIO Port 0 Direction control Lower half-word register. Bit 0 in
FIO0DIRL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C002
Fast GPIO Port 0 Direction control Upper half-word register. Bit 0 in
FIO0DIRU register corresponds to P0.16 ... bit 15 to P0.31.
Section 8.5 "GPIO usage notes" on page 78
Fast GPIO physical pin access control.
Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.
Current state of the pin will be observable in the FIOPIN register.
Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN
registers. When the FIOPIN register is read, this bit will not be updated with
the state of the physical pin.
Rev. 01 — 12 January 2006
UM10161
Chapter 8: GPIO
Reset value
0x0000 0000
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Reset value
0x0000 0000
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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