Gpio Port 0 Output Set Register (Ioset, Port 0: Io0Set - 0Xe002 8004; Fioset, Port 0: Fio0Set - 0X3Fff C018); Koninklijke Philips Electronics N.v. 2006. All Rights Reserved - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 71: GPIO port 0 Pin value register (IO0PIN - address 0xE002 8000) bit description
Bit Symbol Description
31:0 P0xVAL Slow GPIO pin value bits. Bit 0 in IO0PIN corresponds to P0.0 ... Bit 31 in IO0PIN
corresponds to P0.31.
Table 72: Fast GPIO port 0 Pin value register (FIO0PIN - address 0x3FFF C014) bit description
Bit Symbol Description
31:0 FP0xVAL Fast GPIO pin value bits. Bit 0 in FIO0PIN corresponds to P0.0 ... Bit 31 in FIO0PIN
corresponds to P0.31.
Aside from the 32-bit long and word only accessible FIOPIN register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table
registers allow easier and faster access to the physical port pins.
Table 73: Fast GPIO port 0 Pin value byte and half-word accessible register description
Register Register
name length (bits)
& access
FIO0PIN0 8 (byte)
FIO0PIN1 8 (byte)
FIO0PIN2 8 (byte)
FIO0PIN3 8 (byte)
FIO0PINL 16
(half-word)
FIO0PINU 16
(half-word)
8.4.4 GPIO port 0 output Set register (IOSET, Port 0: IO0SET - 0xE002 8004;
FIOSET, Port 0: FIO0SET - 0x3FFF C018)
This register is used to produce a HIGH level output at the port pins configured as GPIO in
an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.
Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing
1 to the corresponding bit in the IOSET has no effect.
Reading the IOSET register returns the value of this register, as determined by previous
writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the
effect of any outside world influence on the I/O pins.
IO0SET is the legacy register while the enhanced GPIOs are supported via the FIO0SET
register. Access to a port pins via the FIOSET register is conditioned by the corresponding
FIOMASK register (see
FIO0MASK - 0x3FFF
User manual
73. Next to providing the same functions as the FIOPIN register, these additional
Address Description
0x3FFF C014 Fast GPIO Port 0 Pin value register 0. Bit 0 in FIO0PIN0 register
corresponds to P0.0 ... bit 7 to P0.7.
0x3FFF C015 Fast GPIO Port 0 Pin value register 1. Bit 0 in FIO0PIN1 register
corresponds to P0.8 ... bit 7 to P0.15.
0x3FFF C016 Fast GPIO Port 0 Pin value register 2. Bit 0 in FIO0PIN2 register
corresponds to P0.16 ... bit 7 to P0.23.
0x3FFF C017 Fast GPIO Port 0 Pin value register 3. Bit 0 in FIO0PIN3 register
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C014 Fast GPIO Port 0 Pin value Lower half-word register. Bit 0 in
FIO0PINL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C016 Fast GPIO Port 0 Pin value Upper half-word register. Bit 0 in
FIO0PINU register corresponds to P0.16 ... bit 15 to P0.31.
Section 8.4.2 "Fast GPIO port 0 Mask register (FIOMASK, Port 0:
C010)").
Rev. 01 — 12 January 2006
UM10161
Chapter 8: GPIO
Reset value
NA
Reset value
NA
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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