Gpio Usage Notes; Example 1: Sequential Accesses To Ioset And Ioclr Affecting The Same Gpio Pin/Bit; Koninklijke Philips Electronics N.v. 2006. All Rights Reserved - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 78: Fast GPIO port 0 output Clear register 0 (FIO0CLR - address 0x3FFF C01C) bit description
Bit Symbol
31:0 FP0xCLR
Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table
registers allow easier and faster access to the physical port pins.
Table 79: Fast GPIO port 0 output Clear byte and half-word accessible register description
Register Register
name length (bits)
& access
FIO0CLR0 8 (byte)
FIO0CLR1 8 (byte)
FIO0CLR2 8 (byte)
FIO0CLR3 8 (byte)
FIO0CLRL 16
(half-word)
FIO0CLRU 16
(half-word)

8.5 GPIO usage notes

8.5.1 Example 1: sequential accesses to IOSET and IOCLR affecting the
same GPIO pin/bit
State of the output configured GPIO pin is determined by writes into the pin's port IOSET
and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine
the final output of a pin.
In case of a code:
IO0DIR = 0x0000 0080 ;pin P0.7 configured as output
IO0CLR = 0x0000 0080 ;P0.7 goes LOW
IO0SET = 0x0000 0080 ;P0.7 goes HIGH
IO0CLR = 0x0000 0080 ;P0.7 goes LOW
pin P0.7 is configured as an output (write to IO0DIR register). After this, P0.7 output is set
to LOW (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to
IO0SET), and the final write to IO0CLR register sets pin P0.7 back to LOW level.
User manual
Description
Fast GPIO output value Clear bits. Bit 0 in FIO0CLR corresponds to P0.0 ... Bit
31 in FIO0CLR corresponds to P0.31.
79. Next to providing the same functions as the FIOCLR register, these additional
Address Description
0x3FFF C01C Fast GPIO Port 0 output Clear register 0. Bit 0 in FIO0CLR0 register
corresponds to P0.0 ... bit 7 to P0.7.
0x3FFF C01D Fast GPIO Port 0 output Clear register 1. Bit 0 in FIO0CLR1 register
corresponds to P0.8 ... bit 7 to P0.15.
0x3FFF C01E Fast GPIO Port 0 output Clear register 2. Bit 0 in FIO0CLR2 register
corresponds to P0.16 ... bit 7 to P0.23.
0x3FFF C01F Fast GPIO Port 0 output Clear register 3. Bit 0 in FIO0CLR3 register
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C01C Fast GPIO Port 0 output Clear Lower half-word register. Bit 0 in
FIO0CLRL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C01E Fast GPIO Port 0 output Clear Upper half-word register. Bit 0 in
FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.
Rev. 01 — 12 January 2006
UM10161
Chapter 8: GPIO
Reset value
0x0000 0000
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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