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Clock source
External
H8/3003 with system
Note
cf dbc
Table 4-1. Clock Speeds(Cont'd)
Chip
Without 64797B
H8/3001
From 0.5 up to 16MHz
H8/3002
H8/3003T
H8/3004
H8/3005
H8/3030
H8/3031
H83032
H8/3040
H8/3041
H8/3042
From 1 up to 24MHz
clock divider
(System clock is from
0.5 up to 12MHz)
Executing this command will drive the emulator into the reset state.
The dbc (drive background cycles) option allows you to select whether
or not the emulator will drive the target system bus on background
cycles.
M> cf dbc=en
You can enable background cycle drive to target system by entering the
above command. Emulation processor's address and control strobes
(except /LWR and /HWR) are driven during background cycles.
Background write cycles won't appear to the target system. (/LWR and
/HWR signals are always "high" when the dbc option is enabled.)
M> cf dbc=dis
If you specify the above command, background monitor cycles are not
driven to the target system.
From 0.5 up to 10MHz
(System clock)
From 1 up to 20MHz
(System clock is from
Configuring the Emulator 4-7
With 64797B
(System clock)
0.5 up to 10MHz)
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