Table of Contents
Advertisement
Table 3-5. Timing condition of On-chip supporting modules (Cont'd)
Characteristics
SCI
Input clock cycle(Async)
Input clock cycle(Sync)
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Received data setup time
Received data hold time
(Clock input)
PORT
Output data delay time
TPC
Input data setup time
Input data hold time
(Vcc = 5.0V, f = 16MHz)
H8/3003
Symbol
Vcc = 5V
f = 16MHz
min
max
t
4
SCYC
t
6
SCYC
t
-
1.5
SCKr
t
-
1.5
SCKf
t
0.4
0.6
SCKw
t
-
100
TXD
t
100
RXS
t
100
RXH
t
-
100
PWD
t
50
PRS
t
50
PRH
*1 Typical outputs measured with 50pF Load
Probe Type
HP 64784E
+
HP 64784x
typ *1
worst typ *1 worst
-
-
-
-
-
-
-
-
-
-
-
-
-
105.8
-
-
136.8
-
-
109.2
-
111.6
-
-
85.9
-
-
37.0
3-19 In-Circuit Emulation
HP 64784D
Unit
-
-
tcyc
-
-
tcyc
-
-
tscyc
-
-
tscyc
-
-
tscyc
-
104.7
ns
-
128.4
ns
-
108.3
ns
-
109.0
ns
-
79.7
ns
-
40.8
ns
Advertisement
Table of Contents
