Clock Generator (Clg); Clock Generator Configuration - Epson S1C17001 Technical Manual

8. Clock Generator (CLG)

8.1 Clock Generator Configuration

The clock generator controls the system clock feed to the S1C17 core and peripheral modules.
Figure 8.1.1 illustrates the clock system and CLG module configuration.
SLEEP, on/off control
OSC3
OSC3
oscillator circuit
(8.2 MHz)
OSC4
FOUT3
FOUT3
output circuit
On/off control
SLEEP, on/off control
OSC1
OSC1
oscillator circuit
(32.768 kHz)
OSC2
FOUT1
FOUT1
output circuit
On/off control
Noise filter
RESET
On/off control
Noise filter
NMI
On/off control
To reduce power consumption, control the clock in conjunction with processing and use standby mode. For more
information on reducing power consumption, refer to "Appendix B: Power Saving."
S1C17001 TECHNICAL MANUAL
OSC
Clock source
wakeup
selection
System
Wait circuit for
OSC3
clock
wakeup
OSC1
Division circuit
(1/1 to 1/4)
Division ratio
selection
S1C17 core
S1C17 core
Figure 8.1.1: CLG module configuration
Gear selection
Gate
Clock gear
(1/1 to 1/8)
Gate
On/off control
Gate
On/off control
Division circuit
Gate
(1/1 to 1/16K)
Division
OSC1
(1/128)
circuit
Gate
(1/1 to 1/32)
Division ratio selection On/off control
EPSON
8 CLOCK GENERATOR (CLG)
CLG
HALT
S1C17 core
CCLK
BCLK Internal bus, RAM,
ROM
HALT
ITC, T16, T8F, UART,
SPI, I2C, T16E, P,
PCLK
MISC, REMC,
Control register (CT,
SWT, WDT, T8OSC1)
PSC
T8F, T16, T16E,
REMC, P, UART, SPI,
I2C
CLK_256Hz CT, SWT, WDT
T8OSC1
71