Epson S1C17001 Technical Manual page 256

D1 MSSL: Master/Slave Mode Select Bit
Sets the SPI module to Master or Slave mode.
1 (R/W): Master mode
0 (R/W): Slave mode (default)
Setting MSSL to 1 selects Master mode; setting it to 0 selects Slave mode. Master mode performs data
transfer with the clock generated by the 16-bit timer Ch.1. In Slave mode, data is transferred by input-
ting the clock from the master device.
D0 SPEN: SPI Enable Bit
Permits or prohibits SPI module operation.
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Setting SPEN to 1 starts the SPI module operation, enabling data transfer.
Setting SPEN to 0 stops the SPI module operation.
Note: The SPEN bit should be set to 0 before setting the CPHA, CPOL, and MSSL bits.
S1C17001 TECHNICAL MANUAL
EPSON
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