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20 I
C
The S1C17 core accepts interrupts when all of the following conditions are met:
• The interrupt enable bit is set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit is set to 1.
• The I
C interrupt has a higher interrupt level set than that set for the PSR IL (interrupt level).
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• There are no other interrupt factors, including NMI, with higher priority.
For detailed information on these interrupt registers and operations when interrupts occur, refer to "6 Interrupt
Controller (ITC)."
Interrupt vectors
The I
C interrupt vector numbers and vector addresses are as listed below.
2
Vector number: 19 (0x13)
Vector address: 0x804c
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EPSON
S1C17001 TECHNICAL MANUAL
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