Epson S1C17001 Technical Manual page 273

2
20 I C
D0 STRT: Start Control Bit
Generates the start condition.
1 (R/W): Start condition generated
0 (R/W): Disabled (default)
With STRT set at 1, the I
while maintaining the I
Set STRT to 1 when data transfer starts.
STRT is automatically reset to 0 once the start condition is generated.
264
2 C module generates the start condition by changing the SDA line to Low
2 C bus SCL line at High. The I
EPSON
2 C bus subsequently becomes busy.
S1C17001 TECHNICAL MANUAL