Epson S1C17001 Technical Manual page 156

Clock output start
To output the TOUT clock, write 1 to OUTEN (D2/T16E_CTL register). Writing 0 to OUTEN switches the
output to the initial output level as set by INITOL and INVOUT.
∗ OUTEN: Clock Output Enable Bit in the PWM Timer Control (T16E_CTL) Register (D2/0x5306)
Figure 13.6.2 illustrates the output waveform.
Counter value
Compare A signal
Compare B signal
TOUT output (INITOL = 0, INVOUT = 0)
TOUT output (INITOL = 0, INVOUT = 1)
TOUT output (INITOL = 1, INVOUT = 0)
TOUT output (INITOL = 1, INVOUT = 1)
When INVOUT = 0 (Active High)
The timer outputs Low level (initial output level at output start) until the counter matches the compare data A
set in the T16E_CA register (0x5300). When the counter reaches the next compare data A value, the output pin
switches to High level, and a compare A interrupt factor is generated. If the counter subsequently counts up to
compare data B set in the T16E_CB register (0x5302), the counter is reset and the output pin is returned to the
Low level. A compare B interrupt factor is also generated at the same time.
When INVOUT = 1 (Active Low)
The timer outputs High level (inverted value of the initial output level at output start) until the counter matches
the compare data A set in the T16E_CA register (0x5300). When the counter reaches the next compare data A
value, the output pin switches to Low level, and a compare A interrupt factor is generated. If the counter subse-
quently counts up to compare data B set in the T16E_CB register (0x5302), the counter is reset and the output
pin is returned to the High level. A compare B interrupt factor is also generated at the same time.
S1C17001 TECHNICAL MANUAL
Input clock
T16ERST
OUTEN
T16ERUN
0
Figure 13.6.2: PWM & capture timer output waveform
13 PWM & CAPTURE TIMER (T16E)
1 2 3 4 5 0 1
(When T16E_CA = 3 and T16E_CB = 5)
EPSON
2 3 4 5 0 1 2 3 4 5 0 1
147