Epson S1C17001 Technical Manual page 265

2
20 I C
Wait state for TXE, RXE, STRT, and STP settings
The module will switch to Wait state with the SCL output fixed at Low if all of the TXE (D9/I2C_DAT regis-
ter), RXE (D10/I2C_DAT register), STRT (D0/I2C_CTL register), and STP (D1/I2C_CTL register) bits are 0
on completion of transfer for 1 byte of data and the ACK. This state is canceled either by writing 1 to TXE or
RXE to restart data transfer or by generating the stop condition with STP.
Prohibiting data transfer
After data transfer is complete (both transmission and receipt), write 0 to the I2CEN bit to prevent data trans-
fers. Confirm that the RBUSY and TBUSY flags are 0 before blocking data transfers.
Data being transferred cannot be guaranteed if I2CEN is set to 0 during the transfer.
Timing chart
Start
Communication start
condition
Register setting
PCLK
T16 Ch.2 output
SCL (input)
SCL (output)
SDA (input)
SDA (output)
STRT
STP
TXE
RXE
TBUSY
RBUSY
RBRDY
RTACK
Shift register
RTDT[7:0]
Interrupt
Figure 20.5.5: I
ACK receipt
PCLK
T16 Ch.2 output
SCL (input)
SCL (output)
SDA (input) ACK
SDA (output) D0
STRT
STP
TXE
RXE
TBUSY
RBUSY
RBRDY
RTACK
Shift register shift
RTDT[7:0] D[7:0]
Interrupt
Figure 20.5.6: I
256
Transmission start
Slave address transmission
A6 A5 A4
valid shift shift shift
A[6:0] + DIR
2
C timing chart 1 (Start condition à Data transmission)
Transmission start
Data continuous transmission
D7 D6 D5
(ACK receipt)
valid shift shift
2 C timing chart 2 (Data transmission à Stop condition)
Transmit data, TXE resetting
A3 A2 A1 A0
shift shift shift
D4 D3 D2
shift shift shift
EPSON
ACK receipt Transmission start
Data transmission
ACK
DIR = 0 D7
(ACK receipt)
shift valid
D[7:0]
Transmission end
Stop
ACK receipt
condition
ACK
D1 D0
(ACK receipt)
shift shift
S1C17001 TECHNICAL MANUAL
D6
shift