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5.
It
response to a parity error (see Section 3:5.2):
The
determination by connecting the PARITY INT signal
to one of10 interrupt lines: VI0 THROUGH VI7, NMI
and PINT.
5.9
STROBE GENERATOR
The
timing pulses used throughout the HRAM board. It also
selects one of the four possible rows of RAM chips
each time the RAM array is accessed.
The basic timing for the Strobe Generator is produced
by a 5-stage delay module which is triggered when the
START
output signals is shown in Figure 5-2.
HRAM
determines
jumper
plug
Strobe
Generator
signal
goes
which
interrupt
in
area
produces
various
high.
The
timing
USER/TECHNICAL MANUAL
to
generate
JP3
makes
this
strobes
of
the
module
in
and
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