Table of Contents
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Section
3.5.1 Designating I/O Port Control Bits
3.5.3 Software Instructions
3.6
Board and Schematic Revision Levels
4 TESTING THE HRAM
5 THEORY OF OPERATION
5.1
5.2
5.3
Refresh Logic
5.4
Port CO Detector
5.5
5.6
Address Decoder
5.7
5.8
Bank and Parity Logic
5.9
5.10
6 TROUBLESHOOTING
6.1
6.2
6.3
Check HRAM Configuration
6.4
Run Diagnostic Programs
6.5
6.6
Repair Procedures
HRAM
USER/TECHNICAL MANUAL
Page___
3-20
3-21
3-22
3-22
5-1
5-2
5-3
5-4
5-4
5-4
5-5
5-5
5-6
5-9
6-1
6-2
6-2
6-2
6-3
6-3
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Table of Contents
