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The Port C0 Detector examines the low order eight bits
of the memory address (A0 through A7) and brings
signal PORT MATCH to a slow level when these bits
contain a hexadecimal C0.
to determine when an output instruction is being
issued to the HRAM board.
5.5
ADDRESS LATCH
The Address Latch stores the upper four bits of the
memory address (A12 through A15) whenever the Central
Processor accesses memory. These bits are used by the
Address Decoders and by the Strobe Generator.
5.6
ADDRESS DECODER
The Address Decoder determines whether this HRAM board
will respond to the current memory access.
In
a
examines the upper six bits of the memory address, the
E6 and E8 signals from the Parity and Bank Switching
Logic and the setting of the Memory Address switches
Sl and S2. Signal
allowed to respond to addresses in the range 0000H
through 7FFFH. Signal E$ performs the same function
for the address range 8000H through FFFFH.
The Address Decoder Sets the SEL signal high if the
memory address is within a bank that is switched on
and the corresponding switch in S1 or S2 is turned on.
Memory Address switches are described in Section 3.3.
In a revision D HRAM board, memory address bit A10 is
removed from the Address Decoder input and the OCCLUDE
signal is added in its place. The OCCLUDE signal is
high whenever the memory bank on this HRAM board is
switched off.
The addition of the OCCLUDE signal causes the
following changes in the operation of Memory Address
switch S2:
1.
The switches in S2 operate in pairs rather than
singly.
HRAM
revision
B
HRAM
I
N is low when the HRAM board is
PORT MAT H is used
board,
the
Address
USER/TECHNICAL MANUAL
Decoder
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